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DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26324 is a 16-channel short-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of applications are supported through internal impedance matching. A single bill of material can support E1/T1/J1 with minimum external components. Redundancy is supported through nonintrusive monitoring, optimal high-impedance modes, and configurable 1:1 or 1+1 backup enhancements. An on-chip synthesizer generates the E1/T1/J1 clock rates by a single master clock input of various frequencies. Two clock output references are also offered. The device is offered a 256-pin TEBGA, the smallest package available for a 16-channel LIU.
FEATURES

16 E1, T1, or J1 Short-Haul Line Interface Units Independent E1, T1, or J1 selections Software-Selectable Transmit and Receive-Side Impedance Matching Crystal Less Jitter Attenuator Selectable Single-Rail and Dual-Rail Mode and AMI or HDB3/ B8ZS Line Encoding and Decoding Detection and Generation of AIS Digital/Analog Loss of Signal Detection as per T1.231, G.775, and ETSI 300233 External Master Clock can be Multiple of 2.048 or 1.544MHz for T1/J1 or E1 Operation (This clock will be internally adapted for T1 or E1 Use.) Receiver Signal Level Indicator from -2.5dB to -20dB in 2.5dB Increments Two Built-In BERT Testers for Diagnostics 8-Bit Parallel Interface Support for Intel or Motorola Mode, or 4-Wire Serial Interface Transmit Short-Circuit Protection G.772 Nonintrusive Monitoring Receive Monitor Mode Handles Combinations of 14dB or 20dB of Resistive Attenuation Along with 12dB to 30dB of Cable Attenuation. Specification Compliance to the Latest T1/E1 Standards--ANSI T1.102, AT&T Pub 62411, T1.231, T1.403, ITU G.703, G.742, G.775, G.823, ETSI 300 166, and ETSI 300 233 Single 3.3V Supply with 5V Tolerant I/O JTAG Boundary Scan as per IEEE 1149.1
APPLICATIONS
T1 Digital Cross-Connects ATM and Frame Relay Equipment Wireless Base Stations ISDN Primary Rate Interface E1/T1/J1 Multiplexer and Channel Banks E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
JTAG
SOFTWARE CONTROL AND JTAG
LOSS

RTIP RRING TTIP TRING
RECEIVER TRANSMITTER 1
RPOS RNEG RCLK TPOS TNEG TCLK
ORDERING INFORMATION
PART DS26324G DS26324GN TEMP RANGE 0C to +70C -40C to +85C PIN-PACKAGE 256 TEBGA 256 TEBGA
16
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 070105
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
TABLE OF CONTENTS
1
1.1
STANDARDS COMPLIANCE ........................................................................................................ 6
TELECOM SPECIFICATIONS COMPLIANCE .......................................................................................................... 6
2 3 4 5
5.1
DETAILED DESCRIPTION............................................................................................................. 7 BLOCK DIAGRAMS....................................................................................................................... 8 PIN DESCRIPTION ...................................................................................................................... 10 FUNCTIONAL DESCRIPTION ..................................................................................................... 18
PORT OPERATION ......................................................................................................................................... 18 5.1.1 Serial Port Operation .......................................................................................................................... 18 5.1.2 Parallel Port Operation........................................................................................................................ 19 5.1.3 Interrupt Handling................................................................................................................................ 19 5.2 POWER-UP AND RESET ................................................................................................................................. 20 5.3 MASTER CLOCK ............................................................................................................................................. 20 5.4 TRANSMITTER ............................................................................................................................................... 21 5.4.1 Transmit Line Templates .................................................................................................................... 23 5.4.2 LIU Transmit Front End....................................................................................................................... 26 5.4.3 Dual Rail.............................................................................................................................................. 27 5.4.4 Single-Rail Mode................................................................................................................................. 27 5.4.5 Zero Suppression--B8ZS or HDB3 .................................................................................................... 27 5.4.6 Transmit Power-Down ........................................................................................................................ 27 5.4.7 Transmit All Ones................................................................................................................................ 28 5.4.8 Drive Failure Monitor........................................................................................................................... 28 5.5 RECEIVER ..................................................................................................................................................... 28 5.5.1 Receiver Monitor Mode....................................................................................................................... 28 5.5.2 Peak Detector and Slicer .................................................................................................................... 28 5.5.3 Receive Level Indicator....................................................................................................................... 28 5.5.4 Clock and Data Recovery ................................................................................................................... 29 5.5.5 Loss of Signal...................................................................................................................................... 29 5.5.6 AIS ...................................................................................................................................................... 30 5.5.7 Bipolar Violation and Excessive Zero detector ................................................................................... 31 5.6 JITTER ATTENUATOR ..................................................................................................................................... 31 5.7 G.772 MONITOR ........................................................................................................................................... 32 5.8 LOOPBACKS .................................................................................................................................................. 32 5.8.1 Analog Loopback ................................................................................................................................ 32 5.8.2 Digital Loopback.................................................................................................................................. 33 5.8.3 Remote Loopback ............................................................................................................................... 34 5.9 BERT........................................................................................................................................................... 34 5.9.1 General Description ............................................................................................................................ 34 5.9.2 Configuration and Monitoring.............................................................................................................. 35 5.9.3 Receive Pattern Detection .................................................................................................................. 36 5.9.4 Transmit Pattern Generation............................................................................................................... 38
6
6.1
REGISTER MAPS AND DEFINITION .......................................................................................... 39
REGISTER DESCRIPTION ................................................................................................................................ 48 6.1.1 Primary Register Bank ........................................................................................................................ 48 6.1.2 Secondary Register Bank ................................................................................................................... 60 6.1.3 Individual LIU Register Bank............................................................................................................... 62 6.1.4 BERT Registers .................................................................................................................................. 78
7
7.1 7.2 7.3 7.4 7.5
JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT ................................. 85
TAP CONTROLLER STATE MACHINE............................................................................................................... 86 INSTRUCTION REGISTER ................................................................................................................................ 89 TEST REGISTERS........................................................................................................................................... 90 BOUNDARY SCAN REGISTER .......................................................................................................................... 90 BYPASS REGISTER ........................................................................................................................................ 90 2 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit 7.6 IDENTIFICATION REGISTER ............................................................................................................................. 90
8 9
9.1 9.2 9.3 9.4 9.5
DC ELECTRICAL CHARACTERIZATION ................................................................................... 91 AC TIMING CHARACTERISTICS ................................................................................................ 92
LINE INTERFACE CHARACTERISTICS ............................................................................................................... 92 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS .................................................................................. 93 SERIAL PORT .............................................................................................................................................. 105 SYSTEM TIMING........................................................................................................................................... 106 JTAG TIMING.............................................................................................................................................. 108
10 11 12 13
PIN CONFIGURATION............................................................................................................... 109 PACKAGE INFORMATION........................................................................................................ 110 THERMAL INFORMATION ........................................................................................................ 111 REVISION HISTORY.................................................................................................................. 112
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................... 8 Figure 3-2. Receive Logic Detail.................................................................................................................................. 9 Figure 3-3. Transmit Logic Detail................................................................................................................................. 9 Figure 5-1. Serial Port Operation for Write Access ................................................................................................... 18 Figure 5-2. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 18 Figure 5-3. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 19 Figure 5-4. Interrupt Handling Flow Diagram ............................................................................................................ 20 Figure 5-5. Pre-Scaler PLL and Clock Generator...................................................................................................... 21 Figure 5-6. T1 Transmit Pulse Templates ................................................................................................................. 24 Figure 5-7. E1 Transmit Pulse Templates ................................................................................................................. 25 Figure 5-8. LIU Front End .......................................................................................................................................... 26 Figure 5-9. Jitter Attenuation ..................................................................................................................................... 32 Figure 5-10. Analog Loopback................................................................................................................................... 33 Figure 5-11. Digital Loopback.................................................................................................................................... 33 Figure 5-12. Remote Loopback ................................................................................................................................. 34 Figure 5-13. PRBS Synchronization State Diagram.................................................................................................. 36 Figure 5-14. Repetitive Pattern Synchronization State Diagram ............................................................................... 37 Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 85 Figure 7-2. TAP Controller State Diagram................................................................................................................. 88 Figure 9-1. Intel Nonmuxed Read Cycle ................................................................................................................... 94 Figure 9-2. Intel Mux Read Cycle .............................................................................................................................. 95 Figure 9-3. Intel Nonmux Write Cycle........................................................................................................................ 97 Figure 9-4. Intel Mux Write Cycle .............................................................................................................................. 98 Figure 9-5. Motorola Nonmux Read Cycle .............................................................................................................. 100 Figure 9-6. Motorola Mux Read Cycle ..................................................................................................................... 101 Figure 9-7. Motorola Nonmux Write Cycle .............................................................................................................. 103 Figure 9-8. Motorola Mux Write Cycle ..................................................................................................................... 104 Figure 9-9. Serial Bus Timing Write Operation ........................................................................................................ 105 Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 105 Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 105 Figure 9-12. Transmitter Systems Timing................................................................................................................ 106 Figure 9-13. Receiver Systems Timing ................................................................................................................... 107 Figure 9-14. JTAG Timing ....................................................................................................................................... 108 Figure 10-1.256-Ball TEBGA ................................................................................................................................... 109
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
LIST OF TABLES
Table 4-1. Pin Descriptions........................................................................................................................................ 10 Table 5-1. Parallel Port Mode Selection and Pin Functions ...................................................................................... 19 Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters ............................................ 22 Table 5-3. Registers Related to Control of DS26324 Transmitters ........................................................................... 22 Table 5-4. Template Selections for the DS26324 for Short-Haul Mode .................................................................... 23 Table 5-5. LIU Front-End Values ............................................................................................................................... 27 Table 5-6. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications............................................................... 29 Table 5-7. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications................................................................. 30 Table 5-8. AIS Detection and Reset Criteria ............................................................................................................. 30 Table 5-9. Registers Related to AIS Detection.......................................................................................................... 30 Table 5-10. BPV, Code Violation, and Excessive Zero Error Reporting ................................................................... 31 Table 5-11. Pseudorandom Pattern Generation........................................................................................................ 35 Table 5-12. Repetitive Pattern Generation ................................................................................................................ 35 Table 6-1. Primary Register Set ................................................................................................................................ 40 Table 6-2. Secondary Register Set............................................................................................................................ 41 Table 6-3. Individual LIU Register Set ....................................................................................................................... 42 Table 6-4. BERT Register Set ................................................................................................................................... 43 Table 6-5. Primary Register Set Bit Map ................................................................................................................... 44 Table 6-6. Secondary Register Set Bit Map .............................................................................................................. 45 Table 6-7. Individual LIU Register Set Bit Map.......................................................................................................... 46 Table 6-8. BERT Register Bit Map ............................................................................................................................ 47 Table 6-9. G.772 Monitoring Control (LIU 1) ............................................................................................................. 52 Table 6-10. G.772 Monitoring Control (LIU 9) ........................................................................................................... 53 Table 6-11. TST Template Select Transmitter Register ............................................................................................ 56 Table 6-12. TST Template Select Transmitter Register ............................................................................................ 56 Table 6-13. Template Selection................................................................................................................................. 57 Table 6-14. Address Pointer Bank Selection............................................................................................................. 59 Table 6-15. MCLK Selections for the DS26324......................................................................................................... 65 Table 6-16. Receiver Sensitivity/Monitor Mode Gain Selection ................................................................................ 69 Table 6-17. Receiver Signal Level............................................................................................................................. 70 Table 6-18. Bit Error Rate Transceiver Select for Channels 1-8 .............................................................................. 73 Table 6-19. Bit Error Rate Transceiver Select for Channels 9-16 ............................................................................ 74 Table 6-20. PLL Clock Select .................................................................................................................................... 76 Table 6-21. Clock A Select ........................................................................................................................................ 76 Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 89 Table 7-2. ID Code Structure..................................................................................................................................... 90 Table 7-3. Device ID Codes....................................................................................................................................... 90 Table 8-1. DC Pin Logic Levels ................................................................................................................................. 91 Table 8-2. Pin Capacitance ....................................................................................................................................... 91 Table 8-3. Supply Current and Output Voltage ......................................................................................................... 91 Table 9-1. Transmitter Characteristics....................................................................................................................... 92 Table 9-2. Receiver Characteristics........................................................................................................................... 92 Table 9-3. Intel Read Mode Characteristics .............................................................................................................. 93 Table 9-4. Intel Write Cycle Characteristics .............................................................................................................. 96 Table 9-5. Motorola Read Cycle Characteristics ....................................................................................................... 99 Table 9-6. Motorola Write Cycle Characteristics ..................................................................................................... 102 Table 9-7. Serial Port Timing Characteristics .......................................................................................................... 105 Table 9-8. Transmitter System Timing..................................................................................................................... 106 Table 9-9. Receiver System Timing......................................................................................................................... 107 Table 9-10. JTAG Timing Characteristics................................................................................................................ 108 Table 12-1. Thermal Characteristics........................................................................................................................ 111
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
1 STANDARDS COMPLIANCE
1.1 Telecom Specifications Compliance
The DS26324 LIU meets all the relevant latest Telecommunications Specifications. The following provides the T1 and E1 Specifications and relevant sections that are applicable to the DS26324. * T1-Related Telecommunications Specifications * ANSI T1.102- Digital Hierarchy Electrical Interface * ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring * ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface * G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s * G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy * Pub 62411 High Capacity Terrestrial Digital Service * ITUT G.772 Protected monitoring points provided on digital transmission systems E1-Related Telecommunications Specifications * ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces * ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048 Kbit/s * ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448 Kbit/s * ITUT G.772 Protected monitoring points provided on digital transmission systems * ITUT G.775 Loss of signal (LOS) and alarm indication signal (AIS) defect detection and clearance criteria * ETSI 300 166 Physical and electrical characteristics of hierarchical digital interfaces for equipment using the 2,048 kbit/s-based plesiosynchronous or synchronous digital hierarchies * ETSI 300 233 Integrated Services Digital Network (ISDN) * G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s * G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy * Pub 62411 High Capacity Terrestrial Digital Service
*
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
2 DETAILED DESCRIPTION
The DS26324 is a single-chip, 16-channel, short-haul line interface unit for T1 (1.544Mbps) and E1 (2.048Mbps) applications. Sixteen independent receivers and transmitters are provided in a single TEBGA package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single master reference clock. This clock can be either 1.544MHz or 2.048MHz or multiples thereof, and either frequency can be internally adapted for T1, J1, or E1 mode. Internal impedance matching provided for both transmit and receive paths reduces external component count. The transmit waveforms are compliant to G.703 and T1.102 specification. The DS26324 provides software-selectable internal transmit termination for 100W T1 twisted pair, 110W J1 twisted pair, 120W E1 twisted pair, and 75W E1 coaxial applications. The transmitters have fast high-impedance capability and can be individually powered down. The receivers can function with up to an 18dB receive signal attenuation. A monitor gain setting also can be enabled to provide 14dB and 20dB of resistive gain. The DS26324 can be configured as a 14-channel LIU with channel 1 and 9 used for nonintrusive monitoring in accordance with G.772. The receivers and transmitters can be programmed into single or dual-rail mode. AMI or HDB3/B8ZS encoding and decoding is selectable in single-rail mode. A 128-bit, crystal-less, on-board jitter attenuator for each LIU can be placed in the receive or transmit directions. The jitter attenuator meets the ETSI CTR12/13 ITU G.736, G.742, G.823, and AT&T PUB62411 specifications. The DS26324 detects and generates AIS in accordance with T1.231, G.775, and ETSI 300233. Loss of signal is detected in accordance with T1.231, G.775, and ETSI 300233. The DS26324 can perform digital, analog, remote, and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins. The DS26324 can be configured using 8-bit multiplexed or nonmultiplexed Intel or Motorola ports. A 4-pin serial port selection is also available for configuration and monitoring of the device. The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled into the RTIP and RRING pins of the DS26324. The user has the option to select internal impedance matching to 75W, 100W, 110W, or 120W with the use of a single external resistor. The device recovers clock and data from the analog signal and passes it through a selectable jitter attenuator outputting the received line clock at RCLK and data at RPOS and RNEG. The DS26324 receivers can recover data and clock for up to 18 dB of attenuation of the transmitted signals. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8. Receiver 9 can monitor the performance of receivers 10 to 16 or transmitters 10 to 16. The DS26324 contains 16 identical transmitters. Digital-transmit data is input at TPOS/TNEG with reference to TCLK. The data at these pins can be single rail or dual rail. This data is processed by waveshaping circuitry and the line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask. The DS26324 drives the E1 or T1 line from the TTIP and TRING pins by a 1:2 coupling transformer. The DS26324 supports the use of either a 1:1 or a 1:2 transformer on the receive side through the receiver turns ratio (RTR) bit. Receive internal impedance matching allows one external resistance value to work for all T1/J1/E1 modes.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
3 BLOCK DIAGRAMS
Figure 3-1. Block Diagram
TYPICAL OF ALL 16 CHANNELS
T1CLK E1CLK
DS26324
MUX
VCO/PLL LOS
Optional Termination
Clock/Data Recovery
RRING
Peak Detector
RPOS/RDAT Remote Loopback (Dual Mode) Receive Logic RCLK RNEG/CV
RTIP
Filter
Analog Loopback
Unframed All Ones Insertion
Local Loopback
Jitter Attenuator
Remote Loopback
Line Drivers
CSU Filters
TRING
Wave Shaping
TPOS/TDAT Transmit Logic TCLK TNEG
TTIP OE
Reset
T1CLK
E1CLK
16
16
Reset
Port Interface
Control and Interrupt
JTAG PORT
Master Clock Adapter
5
8
MOTEL
ASB/ALE/SCLK
CLKE
A0 to A4
RDY/ACKB/SDO
D0 to D7/ AD0 to AD7
TRSTB
RSTB
INTB
TMS
CSB
MODESEL
TCLK
TDO
TDI
RDB/RWB
WRB/DSB/SDI
A5/BSWB
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MCLK
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 3-2. Receive Logic Detail
EZDE LOS
RCLK
RCLK
Excessive Zero Detect T1.231
POS IAISEL AISEL
NEG
EN RPOS
B8ZS/HDB3/AMI Decoder (G.703, T1.102) BPVs, Code Violatiions (T1.231, O.161)
ENCODE
NRZ Data
MUX
All Ones Insert (AIS)
RNEG/CV
BPV/CV/EXZ
ENCV
AIS Detector G.775, ETSI 300233, T1.231
ENCODE
CVDEB
CODE
Figure 3-3. Transmit Logic Detail
LCS CODE
SRMS
To Remote Loopback BPV Insert
B8ZS/HDB3/AMI Coder (G.703, T1.102)
MUX
TPOS/ TDATA TNEG/ BPV
ENCODE
BEIR
LASCS
SRMS
MCLK
LCS
TCLK
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
4 PIN DESCRIPTION
Table 4-1. Pin Descriptions
NAME TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TTIP8 TTIP9 TTIP10 TTIP11 TTIP12 TTIP13 TTIP14 TTIP15 TTIP16 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 TRING8 TRING9 TRING10 TRING11 TRING12 TRING13 TRING14 TRING15 TRING16 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RTIP8 RTIP9 RTIP10 RTIP11 RTIP12 RTIP13 RTIP14 RTIP15 RTIP16 PIN E1 F1 K1 L1 T5 T6 T10 T11 M16 L16 G16 F16 A12 A11 A7 A6 E2 F2 K2 L2 R5 R6 R10 R11 M15 L15 G15 F15 B12 B11 B7 B6 A1 C1 H1 N1 T1 T3 T8 T13 T16 P16 J16 D16 A16 A14 A9 A4 TYPE FUNCTION ANALOG TRANSMIT AND RECEIVE
Analog output
Transmit Bipolar Tip for Channels 1-16. These pins are differential line driver Tip outputs. These pins can be high impedance if pin OE is low. When "1" is set in the Output Enable Register OE bit, the associated TTIPn pin will be enabled when the OE pin is high. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. If the TCLK input for a given LIU is held low for 64 MCLKs that LIUs transmitter is powered down and the TTIP/TRING outputs are high impedance.
Analog output
Transmit Bipolar Ring for Channels 1-16. These pins are differential line driver Ring outputs. These pins can be High-Z if pin OE is low. When "1" is set in the Output Enable Register OE bit, the associated TRINGn pin will be enabled when the OE pin is high. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. If the TCLK input for a given LIU is held low for 64 MCLKs that LIUs transmitter is powered down and the TTIP/TRING outputs are high impedance.
Analog input
Receive Bipolar Tip for Channels 1-16. Receive analog input for differential receiver. Data and clock are recovered and output at RPOS/RNEG and RCLK pins respectively. The differential inputs of RTIPn and RRINGn can provide impedance matching with external resistance for E1 75W, E1 120W, T1 100W, or J1 110W.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7 RRING8 RRING9 RRING10 RRING11 RRING12 RRING13 RRING14 RRING15 RRING16 TPOS1/TDATA1 TPOS2/TDATA2 TPOS3/TDATA3 TPOS4/TDATA4 TPOS5/TDATA5 TPOS6/TDATA6 TPOS7/TDATA7 TPOS8/TDATA8 TPOS9/TDATA9 TPOS10/TDATA10 TPOS11/TDATA11 TPOS12/TDATA12 TPOS13/TDATA13 TPOS14/TDATA14 TPOS15/TDATA15 TPOS16/TDATA16 TNEG1 TNEG2 TNEG3 TNEG4 TNEG5 TNEG6 TNEG7 TNEG8 TNEG9 TNEG10 TNEG11 TNEG12 TNEG13 TNEG14 TNEG15 TNEG16 TCLK1 TCLK2 TCLK3 TCLK4 PIN A2 C2 H2 N2 R1 R3 R8 R13 T15 P15 J15 D15 B16 B14 B9 B4 F6 G7 J6 K6 L9 N5 P12 M11 L11 J11 G11 C14 F9 E7 N12 D5 C3 J14 J5 G10 M6 P6 P7 K9 L12 J12 H11 E13 G8 F7 C6 C5 F5 G4 G9 H6 TYPE FUNCTION
Analog Input
Receive Bipolar Ring for Channels 1-16. Receive analog input for differential receiver. Data and clock are recovered and output at RPOS/RNEG and RCLK pins respectively. The differential inputs of RTIPn and RRINGn can provide impedance matching with external resistance for E1 75W, E1 120W, T1 100W, or J1 110W.
DIGITAL Tx/Rx
Transmit Positive Data Input for Channels 1-16. When DS26324 is configured in dual-rail mode, the data input to TPOSn is output as a positive pulse on the line (TIP and Ring). I Transmit Data Input for Channels 1-16. When the device is configured in single-rail mode NRZ data is input to TDATAn. The data is sampled on the falling edge of TCLKn and encoded HDB3/B8ZS or AMI before being output to the line.
Transmit Negative Data for Channels 1-16. When DS26324 is configured in dual-rail mode. The data input to TNEGn is output as a negative mark on the line. TPOS and TNEG in dual-rail mode result in positive and negative pulses sent on the line: TPOSn 0 0 1 1 TNEGn 0 1 0 1 OUTPUT PULSE Space Negative Mark Positive Mark Space
I
I
Transmit Clock for Channels 1-16. The transmit clock must be 1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock used to sample the data TPOS/TNEG or TDAT on the falling edge. The expected TCLK can be inverted. 11 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME TCLK5 TCLK6 TCLK7 TCLK8 TCLK9 TCLK10 TCLK11 TCLK12 TCLK13 TCLK14 TCLK15 TCLK16 RPOS1/RDATA1 RPOS2/RDATA2 RPOS3/RDATA3 RPOS4/RDATA4 RPOS5/RDATA5 RPOS6/RDATA6 RPOS7/RDATA7 RPOS8/RDATA8 RPOS9/RDATA9 RPOS10/RDATA10 RPOS11/RDATA11 RPOS12/RDATA12 RPOS13/RDATA13 RPOS14/RDATA14 RPOS15/RDATA15 RPOS16/RDATA16 RNEG1/CV1 RNEG2/CV2 RNEG3/CV3 RNEG4/CV4 RNEG5/CV5 RNEG6/CV6 RNEG7/CV7 RNEG8/CV8 RNEG9/CV9 RNEG10/CV10 RNEG11/CV11 RNEG12/CV12 RNEG13/CV13 RNEG14/CV14 RNEG15/CV15 RNEG16/CV16 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 RCLK9 PIN M7 L8 L10 P9 K11 K12 F14 E12 C11 D12 N7 D11 F4 F3 L3 L4 K8 M9 P8 M12 M14 K13 G12 E14 C12 C10 C8 E5 E3 G5 K4 M3 L7 M10 P11 K10 M13 L14 F13 F11 E10 C9 C7 J3 D3 G6 K3 K5 P5 M8 P10 P13 L13 TYPE FUNCTION If TCLKn is `high' for 16 or more MCLKs, then transmit all ones (TAOs) is sent to the line side of the corresponding transmit channel. When TCLKn starts clocking again, normal operation will begin again for the corresponding transmit channel. If TCLKn is `low' for 64 or more MCLKs, the corresponding transmit channel on the line side powers down and is put into high impedance. When TCLKn starts clocking again the corresponding transmit channel powers up and comes out of high impedance.
O, tri-state
Receive Positive Data Output for Channels 1-16. In dual-rail mode, the NRZ data output indicates a positive pulse on RTIP/RRING. Upon detecting a LOS, AIS can be inserted if AISEL bit in the GC is set otherwise the pins will be active. AIS insertion can also be controlled on an individual LIU basis by IAISEL register. If a given receiver is in power-down mode the associated RPOS pin is high impedance. Receive Data Output for Channels 1-16. In single-rail mode, NRZ data is sent out on this pin. If a given receiver is in powerdown mode, the associated RPOS pin is high impedance. Note: During an LOS condition, the RPOS/RDATA outputs remain active.
O, tri-state
Receive Negative Data Output for Channels 1-16. In dual-rail mode, the NRZ data output indicates a negative pulse on RTIP/RRING. Upon detecting an LOS, AIS can be inserted if AISEL bit in the GC is set; otherwise, the pins are active. AIS insertion can also be controlled on an individual LIU basis by IAISEL register. If a given receiver is in power-down mode the associated RNEG pin is high impedance. Code Violation for Channels 1-16. In single-rail mode, bipolar violation, code violation, and excessive zeros are reported on CVn. If HDB3 or B8ZS is not selected, this pin indicates only BPVs. If a given receiver is in power-down mode the associated CV pin is high impedance.
O, tri-state
Receive Clock for Channels 1 to 16. The receive data (RPOS/RNEG) is clocked out on the rising edge of RCLK. If a given receiver is in power-down mode the RCLK is high impedance. Upon a LOS being detected, the RCLK is switched from the recovered clock to MCLK. RCLK can be inverted by the RCLKI register.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16 PIN K14 G13 F12 E8 E9 F8 E6 Master Clock. This is an independent free-running clock that can be a multiple of 2.048MHz 50ppm for E1 mode or 1.544MHz 50ppm for T1 mode. The clock selection is available by MC bits MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be internal adapted to 1.544MHz and a multiple of 1.544MHz can be internal adapted to 2.048MHz. Loss of Signal Output. This output goes high when there is no transition on the received signal over a specified interval. The output goes low when there is sufficient ones density in the received signal. The LOS criteria for assertion and desertion criteria are described in Section 5.5.5. The LOS outputs can be configured to comply with T1.231, ITU G.775, or ETSI 300 233. O T1/E1 Clock (TECLK). (Ball E11 only.) This output becomes a T1 or E1 programmable clock output when enabled by register MC. For T1 or E1 frequency selection, see register CCR. Clock A (CLKA). (Ball F10 only.) This output becomes a programmable clock output when enabled by register MC. For frequency options see register CCR. TYPE FUNCTION
MCLK
H12
I
LOS1 LOS2 LOS3 LOS4 LOS5 LOS6 LOS7 LOS8 LOS9 LOS10 LOS11 LOS12 LOS13 LOS14 LOS15/TECLK LOS16/CLKA
D2 G2 J2 M2 R2 T2 R4 R7 R14 N15 K15 H15 B10 B8 E11 F10
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME PIN TYPE HOST SELECTION Mode Selection. This pin is used to select the control mode of the DS26324: Low (R) serial host mode High (R) parallel host mode Motorola Intel Select. When this pin is low Motorola mode is selected. When this pin is high Intel mode is selected. Chip-Select Bar. This signal must be low during all accesses to the registers. Shift Clock. In the serial host mode, this pin is the serial clock. Data on SDI is clocked on the rising edge of SCLK. The data is clocked on SDO on the rising edge of SCLK if CLKE is high. If CLKE is low the data on SDO is clocked on the falling edge of SCLK. SCLK/ALE/ASB N14 I Address Latch Enable. In parallel Intel multiplexed mode, the address lines are latched on the falling edge of ALE. Address Strobe Bar. In parallel Motorola multiplexed mode the address is sampled on the falling edge of ASB. Note: Tie ALE/ASB pin high if using nonmuxed mode. Read Bar. Intel host mode, this pin has to be low for read operation. Read Write Bar. In Motorola mode this pin is low for write operation and high for read operation. Serial Data Input. In the serial host mode, this pin is the serial input SDI. It is sampled on the rising edge of SCLK. Write Bar. In Intel host mode, this pin is active low during write operation. The data or address (multiplexed mode) is sampled on the rising edge of WRB. SDI/WRB/DSB G14 I Data Strobe Bar. In the parallel Motorola mode, this pin is active low. During a write operation the data or address is sampled on the rising edge of DSB. During a read operation the data or address is driven on the rising edge of DSB. In the nonmultiplexed Motorola mode, the address bus (A [5:0]) is latched on the falling edge of DSB. Serial Data Out. In serial host mode, the SDO data is output on this pin. If a serial write is in progress this pin is high impedance. During a read, SDO is high impedance when the SDI is in command/address mode. If CLKE is low, SDO is output on the rising edge of SCLK, if CLKE is high on the falling edge. SD0/RDYB/ACKB C13 O Ready Bar Output. A high on this pin reports to the host that the cycle is not complete and wait states must be inserted. A low means the cycle is complete. Acknowledge Bar. In Motorola parallel mode, a low on this pin indicates that the read data is available for the host or that the written data cycle is complete. 14 of 112 FUNCTION
MODESEL
A3
I
MOTEL CSB
B3 P14
I I
RDB/RWB
H14
I
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME PIN TYPE FUNCTION Interrupt Bar (Active Low). This signal is tri-stated when RST pin is low. This interrupt signal is driven low when an event is detected on any of the enabled interrupt sources in any of the register banks. When there are no active and enabled interrupt sources, the pin can be programmed to either drive high or as open drain. The reset default is open drain when there are no active enabled interrupt sources. All interrupt sources are disabled when RST = 0 and they must be programmed to be enabled. Data Bus 7-0. In nonmultiplexed host mode, these pins are the bidirectional data bus. I/O, tri-state Address/Data Bus 7-0. In multiplexed host mode, these pins are the bidirectional address/data bus. Note: AD7 and AD6 do not carry address information. In serial host mode, these pins should be grounded. Address 5. In the host nonmultiplexed mode, this is the most significant bit of the address bus. A5/BSWP E4 I Bit Swap. In serial host mode, this bit defines the serial data position to be MSB first when low and LSB first when high. In multiplexed host mode, this pin should be grounded. A4 A3 A2 A1 A0 C4 H5 G3 H3 N10 Address Bus 4-0. These five pins are address pins in the parallel host mode. In serial host mode and multiplexed host mode, these pins should be grounded. Output Enable. If this pin is pulled low, all the transmitter outputs (TTIP and TRING) are high impedance. If pulled high, all the transmitters are enabled when the associated Output Enable OE bit is set. OE R12 I If GC.RTCTL is set, the OE pin is granted control of the receiver internal termination. When OE is low, receiver internal termination is high impedance. When OE is high, receiver termination is enabled. The receiver can still monitor incoming signals even when termination is high impedance. Clock Edge. If CLKE is high, SDO is clocked out on falling edge of SCLK and if low SDO is on rising edge of SCLK. Multiplexed/Nonmultiplexed Select Pin. When in parallel port mode, this pin is used to select multiplexed address and data operation or separate address and data. When mux is a high, multiplexed address and data is used and when mux is low, nonmultiplexed is used.
INTB
D7
O, open drain
D7/AD7 D6/AD6 D5/AD5 D4/AD4 D3/AD3 D2/AD2 D1/AD1 D0/AD0
N3 P3 M4 L5 K7 P4 M5 L6
I
CLKE/MUX
T14
I
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME PIN TYPE JTAG TRSTB TMS TCK TDO TDI E15 B13 D14 A15 B15 I, pullup I pullup I O, high-Z I, pullup JTAG Test Port Reset. If low, this pin resets the JTAG port. If it is not used, it can be left floating. JTAG Test Mode Select. This pin is clocked on the rising edge of TCK and is used to control the JTAG selection between scan and test machine control. JTAG Test Clock. The data TDI and TMS are clocked on rising edge of TCK and TDO is clocked out on the falling edge of TCK. JTAG Test Data Out. This is the serial output of the JTAG port. The data is clocked out on the falling edge of TCK. Test Data Input. This pin input is the serial data of the JTAG test. The data on TDI is clocked on the rising edge of TCK. This pin can be left unconnected. RESET RSTB B5 I, pullup Reset Bar. This is the asynchronous reset input bar. It is internally pulled high. A 1ms low on this pin resets the DS26324 registers to default value. POWER SUPPLIES DVDD DVSS VDDT1 VDDT2 VDDT3 VDDT4 VDDT5 VDDT6 VDDT7 VDDT8 VDDT9 VDDT10 VDDT11 VDDT12 VDDT13 VDDT14 VDDT15 VDDT16 H8, J9 H9, J8, R9 D1 G1 J1 M1 T4 T7 T9 T12 N16 K16 H16 E16 A13 A10 A8 A5 I I 3.3V Digital Power Supply Digital Ground FUNCTION
I
3.3V Power Supply for the Transmitter. All VDDT pins must be connected to VDDT, which has to be 3.3V.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit NAME GNDT1 GNDT2 GNDT3 GNDT4 GNDT5 GNDT6 GNDT7 GNDT8 GNDT9 GNDT10 GNDT11 GNDT12 GNDT13 GNDT14 GNDT15 GNDT16 PIN D4 H4 J4 N4 N6 N8 N9 N11 N13 J13 H13 D13 D10 D9 D8 D6 B1, C16, P1, R16, H7, J10 B2, C15, P2, R15, H10, J7 TYPE FUNCTION
I
Analog Ground for Transmitters
AVDD
I
3.3V Analog Core Power Supply. Decouple each pin separately.
AVSS
I
Analog Core Ground
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5 FUNCTIONAL DESCRIPTION
5.1
5.1.1
Port Operation
Serial Port Operation
Setting MODESEL = `low' enables the serial bus interface on the DS26324. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 9.3 for the AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is high and MSB first when BSWP is low. Figure 5-1 to Figure 5-3 show operation with LSB first. This port is compatible with the SPI interface defined for Motorola Processors. An example of this is the MMC2107 from Motorola. Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write (0). The next 6 bits identify the register address (A1 to A6)(A7 is ignored). All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.
Figure 5-1. Serial Port Operation for Write Access
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CSB
SDI 0 (lsb) WRITE ACCESS ENABLED SDO A1 A2 A3 A4 A5 A 6 x (adrs msb) DO (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
Figure 5-2. Serial Port Operation for Read Access with CLKE = 0
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CSB
SDI 0 (lsb) SDO Read Access Enabled A1 A2 A3 A4 A5 A6 X (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-3. Serial Port Operation for Read Access with CLKE = 1
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CSB
SDI 0 (lsb) A1 A2 A3 A4 A5 A6 X
SDO
(msb)
D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
5.1.2
Parallel Port Operation
When using the parallel interface on the DS26324 the user has the option for either multiplexed bus operation or nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26324 can operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following table lists all the pins and their functions in the parallel port mode. See the timing diagrams in Section 9 for more details.
Table 5-1. Parallel Port Mode Selection and Pin Functions
MODESEL, MOTEL, MUX 100 110 101 111 PARALLEL HOST INTERFACE Nonmultiplexed Motorola Nonmultiplexed Intel Multiplexed Motorola Multiplexed Intel ADDRESS, DATA, AND CONTROL CSB, ACKB, DSB, RWB, ASB, A [5:0], D [7:0], INTB CSB, RDYB, WRB, RDB, ALE, A [5:0], D [7:0], INTB CSB, ACKB, DSB, RWB, ASB, AD [7:0], INTB CSB, RDYB, WRB, RDB, ALE, AD [7:0], INTB
5.1.3
*
Interrupt Handling
There are 4 sets of events that can potentially trigger an Interrupt. The interrupt functions as follows: When status changes on an interruptible event, INTB pin will go low if the event is enabled through the corresponding Interrupt Enable Register. The INTB has to be pulled high externally with a 10 KW resister for wired-OR operation. If a wired-OR operation is not required, the INTB pin can be configured to be High when not active by setting register GISC.INTM. When an Interrupt occurs the Host Processor has to read the Interrupt Status register to determine the source of the Interrupt. The read will also clear the Interrupt Status register and this will clear the output INTB pin. The Interrupt Status register can also be configured as clear on write as per register GISC.CWE. When set to clear on write, and interrupt status register bit (and the interrupt it generates) will only be cleared on writing a `1' to it's bit location in the interrupt status register. This makes is possible to clear interrupts on some bits in a register without clearing them on all bits. Subsequently the host processor can read the corresponding Status Register to check the real-time status of the event.
*
*
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-4. Interrupt Handling Flow Diagram
Interrupt Allowed
No
Interrupt Conditon Exist?
Yes
Read Interrupt Status Register
Read Corresponding Status Register (Optional)
Service the Interrupt
5.2
Power-Up and Reset
Internal Power_On_Reset circuitry generates a reset during power-up. All Registers are reset to the default values. Writing to the Software Reset Register generates at least 1-microsecond reset cycle, which has the same effect as the power-up reset. The DS26324 can be reset by a low going pulse on the RSTB pin (see Table 4-1). A reset can also be performed in software by writing any value to the SWR register.
5.3
Master clock
The DS26324 requires 2.048MHz 50ppm or 1.544MHz 50ppm or multiple thereof. The receiver uses the MCLK as a reference for clock recovery, jitter attenuation and generating RCLK during LOS. The AIS Transmission uses MCLK for Transmit All Ones Condition. See register MC to set desired incoming frequency. When the PLLE bit is set, the master clock adapter will generate both 2.048MHz (E1) and 1.544MHz (T1) clocks. If the PLLE bit is clear, both internal reference clocks will track MCLK. MCLK or RCLK can also be used to output CLKA on the LOS16 pin. Register CCR is used to select the clock generated for CLKA and the TECLK. Any RCLK can also be selected as an input to the clock generator using this same register. For a detailed description of selections available, see Figure 5-5.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-5. Pre-Scaler PLL and Clock Generator
PCLKS2..0
RLCK1..8
PLLE
CLKA3..0
RLOS16 T1CLK MPS1..0 FREQS PCLKI1..0 CLKAE
MCLK
Pre Scaler PLL
PLLE
CLK GEN
E1CLK
LOS16 CLKA
TECLK LOS15
TECLKS RLCK9..16 RLOS15
TECLKE
PCLKS2..0
5.4
Transmitter
NRZ data arrives on TPOS and TNEG on the Transmit System Side. The TPOS and TNEG data is sampled on the falling edge of TCLK. The data is encoded with HDB3 or B8ZS or NRZ encoding when single-rail mode is selected (only TPOS as the data source). When in signal-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Preencoded data is expected when dual-rail mode is selected. The encoded data passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to generate Transmit waveforms compliant with T1.102 and G.703 Pulse Masks. The line driver supports internal impedance matching for 75W, 100W, 110W, and 120W modes. The DS26324 drivers have short and open circuit driver fail monitor detection. There is an OE pin that can High-Z the transmitter outputs for Protection Switching when low. The individual transmitters are by default in High-Z. Register OE is used to enable the transmitters individually when the OE pin is high. The DS26324 has to have the transmitter's enabled by setting the register and then pulling the OE pin high. The registers that control the Transmitter operation are shown in Table 5-2.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 5-2. Telecommunications Specification Compliance for DS26324 Transmitters
TRANSMITTER FUNCTION AMI Coding, B8ZS Substitution, DS1 Electrical Interface T1 Telecom Pulse Mask compliance T1 Telecom Pulse Mask compliance Transmit Electrical Characteristics for E1 Transmission and Return Loss Compliance TELECOMMUNICATIONS COMPLIANCE ANSI T1.102 ANSI T1.403 ANSI T1.102 ITUT G.703.
Table 5-3. Registers Related to Control of DS26324 Transmitters
REGISTER NAME Transmit All Ones Enable Driver Fault Monitor Status Driver Fault Monitor Interrupt Enable Driver Fault Monitor Interrupt Status Automatic Transmit All Ones Select Global Configuration Register Template Select Transmitter Template Select Output Enable Configuration Register Master Clock Selection Transmit Single-Rail Mode Select Register Line Code Selection Transmit Power-down Individual Jitter Attenuator Enable Individual Jitter Attenuator Position Select Individual Jitter Attenuator FIFO Depth Select Individual Jitter Attenuator FIFO Limit Trip Individual Short Circuit Protection Disable BERT Control Register Transmit clock invert BPV Error insertion ACRONYM TAOE DFMS DFMIE DFMIS ATAOS GC TST TS OE MC SRMS LCS TPDE IJAE IJAPS IJAFDS IJAFLT ISCPD BTCR TCLKI BEIR FUNCTION Transmit All Ones Enable Driver Fault Status Driver Fault Status Interrupt Mask Driver Fault Status Interrupt Mask Transmit all ones enabled automatically on LOS Global control of Jitter Attenuator, line coding and short circuit protection. The Transmitter that the Template Select Register Applies to. The TS2 to TS0 bits for Selection of the Templates for Transmitter and TIMPOFF and TIMPRIM bits to control transmit impedance match These register bits can be used to enable the Transmitter outputs Selects the MCLK frequency used for Transmit and Receive. This register can be used to select between single-rail and dual-rail mode. The individual Transceiver Line Codes can be selected to overwrite the global setting. Individual Transmitters can be powered down. Enables the jitter attenuator Selects whether jitter attenuator is in transmit or receive path Selects depth of jitter attenuator FIFO. Indicates jitter attenuator FIFO within 4 bits of its useful limit This register allows the individual Transmitters to have Short Circuit Protection Disable. This register allows mapping of the internal BERTs into an individual transmit path. Inverts TCLK input. Inserts a bipolar error in the transmit path when in single-rail mode.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.4.1
Transmit Line Templates
The DS26324 transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse Mask is shown in the Transmit Pulse Template and can be configured on an individual LIU basis. The transmit template is selected via the TS2-TS0 bits in the TS register. Transmit impedance matching is selected using the TIMPOFF and the TIMPRM bits of the same register. When transmit impedance matching is enabled TIMPRM will select between 75W and 120W impedance if an E1 template is selected, and between 100W and 110W impedance if a T1/J1 template is selected. In E1 mode if 75W is selected via the TIMPRM bit, the output pulse amplitude will be 2.37V, if 120W is selected via the TIMPRIM bit, the output pulse amplitude will be 3.0V. The E1 pulse template is shown in Figure 5-7 and the T1 pulse template is shown in Figure 5-6.
Table 5-4. Template Selections for the DS26324 for Short-Haul Mode
TS2, TS1, TS0 000 001 010 011 100 101 110 111 APPLICATION E1 Reserved DSX-1 (0-133 ft) DSX-1 (133-266 ft) DSX-1 (266-399 ft) DSX-1 (399-533 ft) DSX-1 (533-655 ft)
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-6. T1 Transmit Pulse Templates
1 .2 1 .1 1 .0 0 .9 0 .8 0 .7
NRA O M LIZEDA PLITU E M D
0 .6 0 .5 0 .4 0 .3 0 .2 0 .1 0 -0 .1 -0 .2 -0 .3 -0 .4 -0 .5 -5 0 0 -4 0 0 -3 0 0 -2 0 0 -1 0 0 0 100 200 T IM E (n s ) 300 400 500 600 700
T 1 .1 0 2 / 8 7 , T 1 .4 0 3 , C B 1 1 9 (O c t. 7 9 ), & I.4 3 1 T e m p la te
D S X -1 T e m p la te (p e r A N S I T 1 .1 0 2 -1 9 9 3 )
M A X IM U M C U R V E UI T im e Am p. - 0 .7 7 - 0 .3 9 - 0 .2 7 - 0 .2 7 - 0 .1 2 0 .0 0 0 .2 7 0 .3 5 0 .9 3 1 .1 6 -5 0 0 -2 5 5 -1 7 5 -1 7 5 -7 5 0 175 225 600 750 0 .0 5 0 .0 5 0 .8 0 1 .1 5 1 .1 5 1 .0 5 1 .0 5 - 0 .0 7 0 .0 5 0 .0 5 M IN IM U M C U R V E UI T im e Am p. - 0 .7 7 - 0 .2 3 - 0 .2 3 - 0 .1 5 0 .0 0 0 .1 5 0 .2 3 0 .2 3 0 .4 6 0 .6 6 0 .9 3 1 .1 6 -5 0 0 -1 5 0 -1 5 0 -1 0 0 0 100 150 150 300 430 600 750 - 0 .0 5 - 0 .0 5 0 .5 0 0 .9 5 0 .9 5 0 .9 0 0 .5 0 - 0 .4 5 - 0 .4 5 - 0 .2 0 - 0 .0 5 - 0 .0 5
D S 1 T e m p l a t e ( p e r A N S I T 1 .4 0 3 - 1 9 9 5 )
M A X IM U M C U R V E UI T im e Am p. - 0 .7 7 - 0 .3 9 - 0 .2 7 - 0 .2 7 - 0 .1 2 0 .0 0 0 .2 7 0 .3 4 0 .7 7 1 .1 6 -5 0 0 -2 5 5 -1 7 5 -1 7 5 -7 5 0 175 225 600 750 0 .0 5 0 .0 5 0 .8 0 1 .2 0 1 .2 0 1 .0 5 1 .0 5 - 0 .0 5 0 .0 5 0 .0 5 M IN IM U M C U R V E UI T im e Am p. - 0 .7 7 - 0 .2 3 - 0 .2 3 - 0 .1 5 0 .0 0 0 .1 5 0 .2 3 0 .2 3 0 .4 6 0 .6 1 0 .9 3 1 .1 6 -5 0 0 -1 5 0 -1 5 0 -1 0 0 0 100 150 150 300 430 600 750 - 0 .0 5 - 0 .0 5 0 .5 0 0 .9 5 0 .9 5 0 .9 0 0 .5 0 - 0 .4 5 - 0 .4 5 - 0 .2 6 - 0 .0 5 - 0 .0 5
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-7. E1 Transmit Pulse Templates
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.4.2
LIU Transmit Front End
It is recommended that the LIU for the transmitter be configured as described in Figure 5-8 and in Table 5-5.
Figure 5-8. LIU Front End
3.3V TVDDn C1 C2 TTIP Dt Ct Dt TVSSn TRING Dt 3.3V (One Channel) AVDDn C3 C4
A75 A100 A110
Dt
TFt 1:2 Tx Line
RTIP C5 Rt Rt
Dt Dt Dt Dt
TFr 1:1 or 1:2 Rx Line
AVSSn 3.3V
TVS1
RRING
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 5-5. LIU Front-End Values
MODE Tx Capacitance Tx Protection Rx Transformer RTR 1:1 Tx Transformer 1:2 Rx Transformer RTR 1:2 Tx Transformer 1:2 Tx Decoupling (TVDDn) Tx Decoupling (TVDDn) Rx Decoupling (AVDD) Rx Decoupling (AVDD) Rx Termination Rx Termination RTR 1:1 Rx Termination RTR 1:2 Voltage Protection
1
COMPONENT Ct Dt
1
TFr TFt TFr TFt C1 C2 C3 C4 1 C5 1 Rt 1 Rt TVS1
75W COAX, 120W TWISTED PAIR, 100/110W TWISTED PAIR 560pF typical. Adjust for board parasitics for optimal return loss. International Rectifier 11DQ04 or 10BQ060 Motorola MBR0540T1 Pulse TX1475 Halo TG83-S005NU Pulse T1124 (0C to +70C) Pulse T1114 (-40C to +85C) Common decoupling for all 16 channels = 68mF. Recommended decoupling per channel = 0.1mF. Common decoupling for all 16 channels = 68mF. Decouple all six pins separately with a 0.1mF capacitor. Rx capacitance for all 16 channels = 0.1mF. Needed two resistors for all modes = 60.4W 1%. Needed two resistors for all modes = 15.0W 1%. SGS-Thomson SMLVT 3V3 (3.3V Transient Suppressor)
Only use if necessary for application.
5.4.3
Dual Rail
Dual-rail mode consists of TPOS, TNEG and TCLK pins on the System side. NRZ data is sampled on the falling edge of TCLK as shown in Figure 9-12. The Zero substitution B8ZS or HDB3 is not allowed. The data that appears on the TPOS pin will be output on TTIP and data on the TNEG will be output on TRING after pulse shaping. SingleRail Select Register (SRMS) is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS and TNEG can be overwritten in the maintenance mode by setting the BERT Control Register (BTCR).
5.4.4
Single-Rail Mode
Single-rail mode consists of TPOS, TNEG and TCLK pins on the system side. NRZ data is sampled on the falling edge of TCLK as shown in Figure 9-12. The Zero substitution B8ZS or HDB3 is allowed. The TPOS data will be encoded in AMI or B8ZS/HDB3 format on the TTIP and TRING pins after pulse shaping. Single-Rail Mode Select (SRMS) is used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS can be overwritten in the maintenance mode by setting in BERT Control Register (BTCR).
5.4.5
Zero Suppression--B8ZS or HDB3
B8ZS coding is available when the device is in T1 mode (selected by TS2, TS1 and TS0 bits in the TS register. B8ZS/HDB3 coding are enabled by default in single-rail mode. Setting the LCS bit in the LCS Register disables B8ZS/HDB3. Note that if the individual LIU is configured in E1 mode then HDB3 code substitution will be selected. Bipolar violations can be inserted via the BEIR register or Transmit Maintenance Register settings only if B8ZS or HDB3 coding is turned off. B8ZS substitution is defined in ANSI T1.102 and HDB3 in ITUT G.703 standards.
5.4.6
Transmit Power-Down
The Transmitter will be powered down if the relevant bits in the TPDE are set. The TTIP/TRING outputs will be High-Z when TPDE is set.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.4.7
Transmit All Ones
When Transmit All Ones is invoked continuous Ones are transmitted using MCLK as the Timing Reference. Data input at TPOS and TNEG is ignored. Transmit All ones can be sent by setting bits in the TAOE Register. Also Transmit All ones will be enabled if bits in Register ATAOS are set and the corresponding receiver goes into LOS state in status register LOSS.
5.4.8
Drive Failure Monitor
The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short or Open Circuit on the Secondary side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected. The DFMS status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver failure.
5.5
Receiver
The 16 receivers of DS26324 are all identical. Either a 2:1 or 1:1 transformer can be used on the receive side (selected by the RTR bit). The DS26324 is designed to be fully software-selectable for E1 and T1/J1 without the need to change any external resistors for the receive-side. The receive impedance match settings are controlled by the transmit template/impedance selection. See Figure 5-8 and Table 5-5 for external component values. Internal impedance matching is enabled via the RIMPON bit. The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery system derives E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding performance to meet jitter tolerance specifications. Dependent on selection options B8ZS/HDB3/AMI decoding is performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection of single rail or dual rail is done by settings in the SRMS register. The receiver is capable of recovering signals up to 18dB worth of attenuation. The receiver contains functionality to provide resistive gain up to 20dB for monitor mode.
5.5.1
Receiver Monitor Mode
The receive equalizer is equipped with a monitor mode function that allows for resistive gain up to 20dB along with cable attenuation of 6dB to 24dB as shown in the RSMM1-4 register.
5.5.2
Peak Detector and Slicer
The Slicer determines the polarity and presence of the received data. The output of the Slicer is sent to the Clock and Data Recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination of the slicing threshold.
5.5.3
Receive Level Indicator
The DS26324 will report the signal strength at RTIP and RRING in increments described in Table 6-18 via register bits CnRL3-CnRL0 located in the RSL1-4 register.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.5.4
Clock and Data Recovery
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding performance to meet jitter tolerance specifications.
5.5.5
Loss of Signal
The DS26324 uses both the Digital and Analog loss detection method in compliance with the latest T1.231 for T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation. LOS is detected if the receiver level falls bellow a threshold analog voltage for a certain duration. Alternatively this can be termed as having received "zeros" for certain duration. The signal level and timing duration are defined in accordance with the T1.231 or G.775 or ETSI 300 233 specifications. The Loss Detection Thresholds are based on cable loss of 18dB for both T1 and E1 modes. RCLK is replaced by MCLK when the receiver detects a Loss of signal. If the AISEL bit is set in the GC register or the IAISEL bit is set, the RPOS/RNEG data is replaced by AIS. The loss state is exited when the receiver detects a certain number of ones density at a higher signal level than the loss detection level. The loss detection signal level and loss reset signal level are defined with a hysteresis to prevent the receiver from bouncing between "LOS" and "no LOS" states. The following Table outlines the specifications governing the loss function:
Table 5-6. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications
CRITERIA Loss Detection Criteria T1.231 No pulses are detected for 175 75 bits. Loss is terminated if a duration of 12.5% ones are detected over duration of 175 75 bits. Loss is not terminated if 8 consecutive zeros are found if B8ZS encoding is used. If B8ZS is not used loss is not terminated if 100 consecutive pulses are zero. STANDARD ITU G.775 No pulses are detected for duration of 10 to 255 bit periods. ETSI 300 233 No pulses are detected for a duration of 2048 bit periods or 1ms.
Loss Reset Criteria
The incoming signal has transitions for duration of 10 to 255 bit periods.
Loss reset criteria is not defined.
5.5.5.1
4.5.3.1 ANSI T1.231 for T1 and J1 Modes
Loss is detected if the received signal level is less than 200mV for duration of 192 bit periods. LOS is reset if the all of the following criteria are met: * * * 5.5.5.2 24 or more ones are detected in 192-bit period with a detection threshold of 300mV measured at RTIP and RRING. During the 192 bits less than 100 consecutive zeros are detected. 8 consecutive zeros are not detected if B8ZS is set. 4.5.3.1 ITU G.775 for E1 Modes
LOS is detected if the received signal level is less than 200mV for a continuous duration of 192 bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods. 5.5.5.3 4.5.3.1 ETSI 200 233 for E1 Modes
LOS is detected if the received signal level is less than 200mV for a continuous duration of 2048 (1ms) bit periods. LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.5.6
AIS
Table 5-7 outlines the DS26324 AIS related specifications. Table 5-8 states the AIS functionality in the DS26324. The registers related to the AIS detection are shown in Table 5-9.
Table 5-7. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications
CRITERIA AIS Detection Criteria AIS Clearance Criteria ITU G.775 for E1 2 or fewer zeros in each of 2 consecutive 512-bit streams received. 3 or more zeros in each of 2 consecutive 512-bit streams received. STANDARD ETSI 300233 for E1 Less than 3 zeros detected in 512-bit period. 3 or more zeros in a 512 bits received. ANSI T1.231 for T1 Fewer than 9 zeros detected in a 8192-bit period (a ones density of 99.9% over a period of 5.3ms) are received. 9 or more zeros detected in a 8192-bit period are received.
Table 5-8. AIS Detection and Reset Criteria
CRITERIA AIS Detection Criteria AIS Clearance Criteria ITU G.775 for E1 2 or less zeros in each of 2 consecutive 512-bit streams received. 3 or more zeros in each of 2 consecutive 512-bit streams received. STANDARD ETSI 300233 for E1 Less than 3 zeros detected in 512-bit period. 3 or more zeros in 512 bits received. ANSI T1.231 for T1 Fewer than 9 zeros contained in 8192 bits. 9 or more bits received in a 8192-bit stream.
Table 5-9. Registers Related to AIS Detection
REGISTER LOS/AIS Criteria AIS Register AIS Enable Register AIS Interrupt ACRONYM POINTER LASCS AIS AISIE AISI FUNCTIONALITY Section criteria for AIS (T1.231, G.775, ETSI 300233 for E1) Set when AIS is detected. If reset interrupt due to AIS is not generated. Latched if there is a change in AIS and the interrupt is enabled.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.5.7
Bipolar Violation and Excessive Zero detector
DS26324 detects code violations, BPV and excessive zero errors. The reporting of the errors is done through the pin RNEGn/CVn. Excessive zeros are detected if 8 consecutive zeros are detected with B8ZS enabled and 4 consecutive zeros are detected with HDB3 enabled. Excessive Zero detection is selectable when single-rail mode and HDB3/B8ZS encoding/decoding is selected. The bits in EZDE and CVDEB registers determine the combinations that are reported. Table 5-10 outlines the functionality:
Table 5-10. BPV, Code Violation, and Excessive Zero Error Reporting
CONDITIONS EZDE is reset, CVDEB is reset EZDE is set, CVDEB is reset EZDE is reset, CVDEB is set EZDE is set, CVDEB is set CVn PIN REPORTS BPV + Code violation BPV + Code violation + Excessive zero BPV BPV + Excessive zero
5.6
Jitter Attenuator
The DS26324 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits via the JADS bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register. The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 5-9. The jitter attenuator can be placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE bits in register GC. These selections can be changed on an individual LIU basis by settings in the IJAPS and IJAE. In order for the jitter attenuator to operate properly, a 2.048MHz or multiple thereof or 1.544MHz clock or multiple thereof must be applied at MCLK. ITU specification G.703 requires an accuracy of 50ppm for both T1 and E1 Applications. TR62411 and ANSI specs require an accuracy of 32ppm for T1 interfaces. On-board circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a jittery clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the DS26324 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bits in the IJAFLT register described.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-9. Jitter Attenuation
0dB
TBR12 Prohibited Area ITU G.7XX Prohibited Area
JITTER ATTENUATION (dB)
-20dB
C ve ur A
E1
T1
-40dB
B rve Cu
TR 62411 (Dec. 90) Prohibited Area
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
5.7
G.772 Monitor
In this application, only 14 transceivers are functional and two transceivers are used for nonintrusive monitoring of input and output of the other 14 channels. Channel 9 is used for channels 10 to 16 and Channel 1 is used for channels 2 to 8. G.772 monitoring is configured by GMC registers (see Table 6-9). While monitoring channel 1 can be configured in remote loopback and the monitored signal can be output on TTIP1 and TRING1. While monitoring channel 9 can be configured in remote loopback and the monitored signal can be output on TTIP9 and TRING9.
5.8
Loopbacks
The DS26324 provides 4 loopbacks for diagnostic purposes: analog loopback, digital loopback, remote loopback, and dual loopback. Dual loopback is accomplished by turning on digital loopback and remote loopback at the same time.
5.8.1
Analog Loopback
The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at RTIP and ring is ignored in analog loopback. This is shown in Figure 5-10.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 5-10. Analog Loopback
TCLK TPOS TNEG
HDB3/ B8ZS E ncoder
O p tio n a l J itt e r A tte n u a to r
T r a n s m it D ig it a l
T ra n s m it A n a lo g
Line Driver
RCLK RPOS RNEG
H DB3/ B8ZS D ecoder
O p t io n a l J it te r A tte n u a to r
R e c e iv e D ig i ta l
R e c e iv e A n a lo g
Rtip Rring
5.8.2
Digital Loopback
The transmit system data TPOS and TNEG and TCLK will be looped back to output on RCLK, RPOS and RNEG. The data input at TPOS and TNEG will be encoded and output on TTIP and TRING. Signals at RTIP and RRING will be ignored. This loopback is conceptually shown in Figure 5-11.
Figure 5-11. Digital Loopback
TCLK TPOS TNEG
HDB3/ B8ZS E ncoder
TTIPTPOS
O p tio n a l J itt e r A tte n u a to r
T r a n s m it D ig it a l T ra n s m it A n a lo g
Line Driver TRING TNEG
RCLK RPOS RNEG
H DB3/ B8ZS D ecoder
O p t io n a l J it te r A tte n u a to r
R e c e iv e D ig i ta l
RTIP
R e c e iv e A n a lo g
RRING
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.8.3
Remote Loopback
The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS and TNEG are ignored during a remote loopback. This loopback is conceptually shown in Figure 5-12. Note: Remote loopback does not take precedence over Transmit Power-Down and requires TCLK to operate. The transmitters will use the recovered RCLK in remote loopback. TCLK is still required because if it is removed the transmitters will power-down (TCLK held low) or transmit all ones (TCLK held high).
Figure 5-12. Remote Loopback
TCLK TPOS TNEG
HDB3/ B8ZS E ncoder
TTIP TPOS
O p tio n a l J itt e r A tte n u a to r
T r a n s m it D ig it a l T ra n s m it A n a lo g
Line Driver TRING TNEG
RCLK RPOS RNEG
H DB3/ B8ZS D ecoder
O p t io n a l J it te r A tte n u a to r
R e c e iv e D ig i ta l
RTIP
R e c e iv e A n a lo g
RRING
5.9
BERT
There are two bit error rate testers available on the DS26324. One BERT can be mapped into LIUs 1-8 and the other into LIUs 9-16 via the BTCR registers. The two BERTs operate independently of each other.
5.9.1
General Description
The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. It will generate and synchronize to pseudorandom n y patterns with a generation polynomial of the form x + x + 1, where n and y can take on values from 1 to 32 and to repetitive patterns of any length up to 32 bits. The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data stream. The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern payload for the programmable test pattern. Features * * * * * Programmable PRBS pattern - The Pseudo Random Bit Sequence (PRBS) polynomial (x + x + 1) and seed n are programmable (length n = 1 to 32, tap y = 1 to n - 1, and seed = 0 to 2 - 1). Programmable repetitive pattern - The repetitive pattern length and pattern are programmable (the length n n = 1 to 32 and pattern = 0 to 2 - 1). 24-bit error count and 32-bit bit count registers Programmable bit error insertion - Errors can be inserted individually, on a pin transition, or at a specific n rate. The rate 1/10 is programmable (n = 1 to 7). -3 Pattern synchronization at a 10 BER - Pattern synchronization will be achieved even in the presence of a -3 random Bit Error Rate (BER) of 10 .
n y
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.9.2
Configuration and Monitoring
Set BTCR.BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send and receive common patterns.
Table 5-11. Pseudorandom Pattern Generation
PATTERN TYPE 2 -1 O.153 (511 type) 11 2 -1 O.152 and O.153 (2047 type) 15 2 -1 O.151 2 -1 O.153 2 -1 O.151 QRSS 2 -1 O.151
23 20 20 9
BPCR REGISTER PTF[4:0] PLF[4:0] PTS (hex) (hex) 04 08 0 08 0D 10 02 11 0A 0E 13 13 16 0 0 0 0 0
QRSS 0 0 0 0 1 0
BERT. PCR 0x0408 0x080A 0x0D0E 0x1013 0x0253 0x1116
BERT. SPR2 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
BERT. SPR1 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
BERT.CR TPIC, RPIC 0 0 1 0 0 1
Table 5-12. Repetitive Pattern Generation
PATTERN TYPE All ones All zeros Alternating ones and zeros Double alternating and zeros 3 in 24 1 in 16 1 in 8 1 in 4 PTF[4:0] (hex) NA NA NA NA NA NA NA NA BPCR REGISTER PLF[4:0] PTS (hex) 00 1 00 01 03 17 0F 07 03 1 1 1 1 1 1 1 QRSS 0 0 0 0 0 0 0 0 BERT. PCR 0x0020 0x0020 0x0021 0x0023 0x0037 0x002F 0x0027 0x0023 BERT. SPR2 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFF20 0xFFFF 0xFFFF 0xFFFF BERT. SPR1 0xFFFF 0xFFFE 0xFFFE 0xFFFC 0x0022 0x0001 0xFF01 0xFFF1
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished via a zero-to-one transition on BCR.TNPL and BCR.RNPL Monitoring the BERT requires reading the BSR Register, which contains the Bit Error Count (BEC) bit and the Out of Synchronization (OOS) bit. The BEC bit will be one when the bit error counter is one or more. The OOS will be one when the receive pattern generator is not synchronized to the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64 bit window. The Receive BERT Bit Count Register (RBCR) and the Receive BERT Bit Error Count Register (RBECR) will be updated upon the reception of a Performance Monitor Update signal (e.g. BCR.LPMU). This signal will update the registers with the values of the counters since the last update and will reset the counters.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.9.3
Receive Pattern Detection
The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating n y polynomial x + x + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. Depending on the type of pattern programmed, pattern detection performs either PRBS synchronization or repetitive pattern synchronization. 5.9.3.1 Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be disabled. See Figure 5-13 for the PRBS synchronization diagram.
Figure 5-13. PRBS Synchronization State Diagram
Sync
6o
err ors
f6 4b
out
h wit its
bi t sw ith
ors err
32
1 bit error
Verify
32 bits loaded
Load
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit 5.9.3.2 Receive Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS pattern generator, automatic pattern re-synchronization is initiated. Automatic pattern re-synchronization can be disabled. Figure 5-14 shows the repetitive pattern synchronization state diagram.
Figure 5-14. Repetitive Pattern Synchronization State Diagram
Sync
6o
err ors
f6 4b
out
h wit its
bi t sw ith
ors err
32
1 bit error
Verify
Pattern Matches
Match
5.9.3.3
Receive Pattern Monitoring
Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits. An Out Of Synchronization (OOS) condition is declared when the synchronization state machine is not in the "Sync" state. An OOS condition is terminated when the synchronization state machine is in the "Sync" state. Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit count is incremented. The bit count and bit error count are not incremented when an OOS condition exists.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
5.9.4
Transmit Pattern Generation
Pattern Generation generates the outgoing test pattern, and passes it onto Error Insertion. The transmit pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant n y bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x + x + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all zeros. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to one if bits 1 through 31 are all zeros. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value n before pattern generation starts. The seed/pattern value is programmable (0 - 2 - 1). 5.9.4.1 Transmit Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of n one out of every 10 bits. The value of n is programmable (1 to 7 or off). Single bit error insertion can be initiated from the microprocessor interface, or by the manual error insertion input (TMEI). The method of single error insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
6 REGISTER MAPS AND DEFINITION
Six address bits are used to control the settings of the registers. In the parallel nonmultiplexed mode address [5:0] is used. In multiplexed mode AD [5:0] is used and A [6:1] is used in the serial mode. The register space contains two independent sets of registers. The lower set of registers is located from address 00 hex to 1F hex and contains controls for LIUs 1-8. The upper set of registers is a duplicate of the lower set, located from address 20 hex to 3F hex, which controls LIUs 9-16. Each of these sets of registers consists of 4 banks (Primary, Secondary, Individual LIU, and BERT). The ADDP register for the lower set of registers is located at address 1F hex. This register is used as a pointer to access the 4 banks of registers in the lower (LIUs 1-8) register set. Similarly, the ADDP register for the upper set of registers is located at address 3F hex. This register is used as a pointer to access the 4 banks of registers in the upper (LIUs 9-16) register set. Setting an ADDP register to AA hex will access the Secondary bank of registers, 01 hex will access the Individual LIU bank of registers, 02 hex will access the BERT bank of registers, and 00 hex (default on power-up) will access the Primary bank of registers. Note that bank selection for the lower set of registers is controlled only by the ADDP at 1F hex and that bank selection for the upper set of registers is controlled only by the ADDP at 3F hex.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-1. Primary Register Set
NAME SYMBOL HEX FOR CH 1-8 ADDRESS FOR CH 1-8 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) HEX FOR CH 9-16 ADDRESS FOR CH 9-16 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX)
RW R RW RW RW R R RW RW R R W RW RW RW RW RW RW RW RW R RW R -- RW
Identification Analog Loopback Configuration Remote Loopback Configuration Transmit All Ones Enable LOS Status Driver Fault Monitor Status LOS Interrupt Enable Driver Fault Monitor Interrupt Enable LOS Interrupt Status Driver Fault Monitor Interrupt Status Software Reset G.772 Monitor Configuration Digital Loopback Configuration LOS/AIS Criteria Selection Automatic Transmit All Ones Select Global Configuration Template Select Transceiver Register Template Select Output Enable Alarm Indication Signal AIS Interrupt Enable AIS Interrupt Status Reserved Address Pointer for Bank Selection
ID ALBC RLBC TAOE LOSS DFMS LOSIE DFMIE LOSIS DFMIS SWR GMC DLBC LASCS ATAOS GC TST TS OE AIS AISIE AISIS -- ADDP
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16-1E 1F
xx000000 xx000001 xx000010 xx000011 xx000100 xx000101 xx000110 xx000111 xx001000 xx001001 xx001010 xx001011 xx001100 xx001101 xx001110 xx001111 xx010000 xx010001 xx010010 xx010011 xx010100 xx010101 xx010110- xx011110 xx011111
x000000 x000001 x000010 x000011 x000100 x000101 x000110 x000111 x001000 x001001 x001010 x001011 x001100 x001101 x001110 x001111 x010000 x010001 x010010 x010011 x010100 x010101 x010110- x011110 x011111
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36-3E 3F
Not used xx100001 xx100010 xx100011 xx100100 xx100101 xx100110 xx100111 xx101000 xx101001 xx101010 xx101011 xx101100 xx101101 xx101110 xx101111 xx110000 xx110001 xx110010 xx110011 xx110100 xx110101 xx110110- x111110 xx111111
Not used x100001 x100010 x100011 x100100 x100101 x100110 x100111 x101000 x101001 x101010 x101011 x101100 x101101 x101110 x101111 x110000 x110001 x110010 x110011 x110100 x110101 x110110- x111110 x111111
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-2. Secondary Register Set
HEX FOR CH 1-8 00 01 02 03 04 05 06 07-1E 1F ADDRESS FOR CHANNELS 1-8 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx000000 x000000 xx000001 x000001 xx000010 x000010 xx000011 x000011 xx000100 x000100 xx000101 x000101 xx000110 xx000111- xx011110 xx011111 x000110 x000111- x011110 x011111 HEX FOR CH 9-16 20 21 22 23 24 25 26 27-3E 3F ADDRESS FOR CHANNELS 9-16 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx100000 x100000 xx100001 x100001 xx100010 x100010 xx100011 x100011 xx100100 x100100 xx100101 x100101 xx100110 xx100111- xx111110 xx111111 x100110 x100111- x111110 x111111
NAME
SYMBOL
RW
Single-Rail Mode Select Line Code Selection Not Used Receive Power-Down Enable Transmit Power-Down Enable Excessive Zero Detect Enable Code Violation Detect Enable Bar Not Used Address Pointer for Bank Selection
SRMS LCS -- RPDE TPDE EZDE CVDEB -- ADDP
RW R R RW RW R R W RW
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-3. Individual LIU Register Set
HEX FOR CH 1-8 00 01 02 03 04 05 06 08-0B 0C-0F 10 12 13 14 15 16 1E 1F ADDRESS FOR CHANNELS 1-8 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx000000 x000000 xx000001 x000001 xx000010 xx000011 xx000100 xx000101 xx000110 xx001000- xx001011 xx001100- xx001111 xx010000 xx010010 xx010011 xx010100 xx010101 xx010110 xx011110 xx011111 x000010 x000011 x000100 x000101 x000110 x001000- x001011 x001100- x001111 x010000 x010010 x010011 x010100 x010101 x010110 x011110 x011111 HEX FOR CH 9-16 20 21 22 23 24 25 26 28-2B 2C-2F 30 32 33 34 35 36 3E 3F ADDRESS FOR CHANNELS 9-16 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx100000 x100000 xx100001 x100001 xx100010 xx100011 xx100100 xx100101 Not used xx101000- xx101011 xx101100- xx101111 xx110000 xx110010 xx110011 xx110100 Not used xx110110 Not used xx111111 x100010 x100011 x100100 x100101 Not used x101000- x101011 x101100- x101111 x110000 x110010 x110011 x110100 Not used x110110 Not used x111111
NAME
SYMBOL
RW
Individual JA Enable Individual JA Position Select Individual JA FIFO Depth Select Individual JA FIFO Limit Trip Individual Short Circuit Protection Disable Individual AIS Select Master Clock Select Receive Sensitivity Monitor Mode 1-4 Receive Signal Level Indicator 1-4 Bit Error Rate Tester Control Register Line Violation Detect Status Receive Clock Invert Transmit Clock Invert Clock Control Register RCLK Disable Upon LOS Register Global Interrupt Status Control Address Pointer for Bank Selection
IJAE IJAPS IJAFDS IJAFLT ISCPD IAISEL MC RSMM1-4 RSL1-4 BTCR LVDS RCLKI TCLKI CCR RDULR GISC ADDP
RW RW RW R RW RW RW RW R RW R RW RW RW RW RW RW
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-4. BERT Register Set
HEX FOR CH 1-8 00 01 02 03 04 05 06 07 08 09-0A 0C 0D 0E 10 11-13 14 15 16 17 18 19 1A 1B 1C-1E 1F ADDRESS FOR CHANNELS 1-8 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx000000 x000000 xx000001 x000001 xx000010 x000010 xx000011 x000011 xx000100 x000100 xx000101 x000101 xx000110 x000110 xx000111 x000111 xx001000 x001000 xx001001- -- x001010 xx001100 x001100 xx001101 x001101 xx010011 x010011 xx010000 xx010001- xx010011 xx010100 xx010101 xx010110 xx010111 xx011000 xx011001 xx011010 xx011011 xx011100- xx011110 xx011111 x010000 x010001- x010011 x010100 x010101 x010110 x010111 x011000 x011001 x011010 x011011 x011100- x011110 x011111 HEX FOR CH 9-16 20 21 22 23 24 25 26 27 28 29-2A 2C 2D 2E 30 31-33 34 35 36 37 38 39 3A 3B 3C-3E 3F ADDRESS FOR CHANNELS 9-16 PARALLEL SERIAL INTERFACE INTERFACE A7-A0 A7-A1 (HEX) (HEX) xx100000 x100000 xx100001 x100001 xx100010 x100010 xx100011 x100011 xx100100 x100100 xx100101 x100101 xx100110 x100110 xx100111 x100111 xx101000 x101000 xx101001- -- x101010 xx101100 x101100 xx101101 x101101 xx110011 x110011 xx110000 xx110001- xx110011 xx110100 xx110101 xx110110 xx110111 xx111000 xx111001 xx111010 xx111011 xx111100- xx111110 xx111111 x110000 x110001- x110011 x110100 x110101 x110110 x110111 x111000 x111001 x111010 x111011 x111100- x111110 x111111
NAME
SYMBOL
RW
BERT Control Register Reserved BERT Pattern Configuration 1 BERT Pattern Configuration 2 BERT Seed/Pattern 1 BERT Seed/Pattern 2 BERT Seed/Pattern 3 BERT Seed/Pattern 4 Transmit Error Insertion Control Reserved BERT Status Register Reserved BERT Status Register Latched BERT Status Register Interrupt Enable Reserved Receive Bit Error Count Register 1 Receive Bit Error Count Register 2 Receive Bit Error Count Register 3 Receive Bit Error Count Register 4 Receive Bit Count Register 1 Receive Bit Count Register 2 Receive Bit Count Register 3 Receive Bit Count Register 4 Reserved Address Pointer for Bank Selection
BCR -- BPCR1 BPCR2 BSPR1 BSPR2 BSPR3 BSPR4 TEICR -- BSR BSRL BSRIE -- RBECR1 RBECR2 RBECR3 RBECR4 RBCR1 RBCR2 RBCR3 RBCR4 -- ADDP
RW RW RW RW RW RW RW RW -- R RW RW -- R R R R R R R R -- RW
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-5. Primary Register Set Bit Map
REGISTER
ID ALBC RLBC TAOE LOSS DFMS LOSIE DFMIE LOSIS DFMIS SWR GMC DLBC LASCS ATAOS GC TST TS OE AIS AISIE AISI Not Used ADDP
ADDRESS FOR LIUS 1-8
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16-1E 1F
R/W
R RW RW RW RW RW RW RW R R W RW RW RW RW RW RW RW RW R RW R -- RW
BIT 7
ID7 ALC8 RLBC8 TAOE8 LOSS8 DFMS8 LOSIE8 DFMIE8 LOSIS8 DFMIS8 SWRL -- DLBC8 LASCS8 ATAOS8 -- -- RIMPON OE8 AIS8 AISIE8 AISI8 -- ADDP7
BIT 6
ID6 ALBC7 RLBC7 TAOE7 LOSS7 DFMS7 LOSIE7 DFMIE7 LOSIS7 DFMIS7 SWRL -- DLBC7 LASCS7 ATAOS7 AISEL -- TIMPOFF OE7 AIS7 AISIE7 AISI7 -- ADDP6
BIT 5
ID5 ALBC6 RLBC6 TAOE6 LOSS6 DFMS6 LOSIE6 DFMIE6 LOSIS6 DFMIS6 SWRL -- DLBC6 LASCS6 ATAOS6 SCPD -- -- OE6 AIS6 AISIE6 AISI6 -- ADDP5
BIT 4
ID4 ALBC5 RLBC5 TAOE5 LOSS5 DFMS5 LOSIE5 DFMIE5 LOSIS5 DFMIS5 SWRL -- DLBC5 LASCS5 ATAOS5 CODE -- -- OE5 AIS5 AISIE5 AISI5 -- ADDP4
BIT 3
ID3 ALBC4 RLBC4 TAOE4 LOSS4 DFMS4 LOSIE4 DFMIE4 LOSIS4 DFMIS4 SWRL GMC4 DLBC4 LASCS4 ATAOS4 JADS -- TIMPRM OE4 AIS4 AISIE4 AISI4 -- ADDP3
BIT 2
ID2 ALBC3 RLBC3 TAOE3 LOSS3 DFMS3 LOSIE3 DFMIE3 LOSIS3 DFMIS3 SWRL GMC3 DLBC3 LASCS3 ATAOS3 RTCTL TST2 TS2 OE3 AIS3 AISIE3 AISI3 -- ADDP2
BIT 1
ID1 ALBC2 RLBC2 TAOE2 LOSS2 DFMS2 LOSIE2 DFMIE2 LOSIS2 DFMIS2 SWRL GMC2 DLBC2 LASCS2 ATAOS2 JAPS TST1 TS1 OE2 AIS2 AISIE2 AISI2 -- ADDP1
BIT 0
ID0 ALBC1 RLBC1 TAOE1 LOSS1 DFMS1 LOSIE1 DFMIE1 LOSIS1 DFMIS1 SWRL GMC1 DLBC1 LASCS1 ATAOS1 JAE TST0 TS0 OE1 AIS1 AISIE1 AISI1 -- ADDP0
REGISTER
Not Used ALBC RLBC TAOE LOSS DFMS LOSIE DFMIE LOSIS DFMIS SWR GMC DLBC LASCS ATAOS GC TST TS OE AIS AISIE AISI Not Used ADDP
ADDRESS FOR LIUs 9-16
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36-3E 3F
R/W
R RW RW RW RW RW RW RW R R W RW RW RW RW RW RW RW RW R RW R -- RW
BIT 7
-- ALC16 RLBC16 TAOE16 LOSS16 DFMS16 LOSIE16 DFMIE16 LOSIS16 DFMIS16 SWRU -- DLBC16 LASCS16
ATAOS16
BIT 6
-- ALBC15 RLBC15 TAOE15 LOSS15 DFMS15 LOSIE15 DFMIE15 LOSIS15 DFMIS15 SWRU -- DLBC15 LASCS15
ATAOS15
BIT 5
-- ALBC14 RLBC14 TAOE14 LOSS14 DFMS14 LOSIE14 DFMIE14 LOSIS14 DFMIS14 SWRU -- DLBC14 LASCS14
ATAOS14
BIT 4
-- ALBC13 RLBC13 TAOE13 LOSS13 DFMS13 LOSIE13 DFMIE13 LOSIS13 DFMIS13 SWRU -- DLBC13 LASCS13
ATAOS13
BIT 3
-- ALBC12 RLBC12 TAOE12 LOSS12 DFMS12 LOSIE12 DFMIE12 LOSIS12 DFMIS12 SWRU GMC4 DLBC12 LASCS12
ATAOS12
BIT 2
-- ALBC11 RLBC11 TAOE11 LOSS11 DFMS11 LOSIE11 DFMIE11 LOSIS11 DFMIS11 SWRU GMC3 DLBC11 LASCS11
ATAOS11
BIT 1
-- ALBC10 RLBC10 TAOE10 LOSS10 DFMS10 LOSIE10 DFMIE10 LOSIS10 DFMIS10 SWRU GMC2 DLBC10 LASCS10
ATAOS10
BIT 0
-- ALBC9 RLBC9 TAOE9 LOSS9 DFMS9 LOSIE9 DFMIE9 LOSIS9 DFMIS9 SWRU GMC1 DLBC9 LASCS9
ATAOS9
-- -- RIMPON OE16 AIS16 AISIE16 AISI16 -- ADDP7
AISEL -- TIMPOFF OE15 AIS15 AISIE15 AISI15 -- ADDP6
SCPD -- -- OE14 AIS14 AISIE14 AISI14 -- ADDP5
CODE -- -- OE13 AIS13 AISIE13 AISI13 -- ADDP4
JADS -- TIMPRM OE12 AIS12 AISIE12 AISI12 -- ADDP3
-- TST2 TS2 OE11 AIS11 AISIE11 AISI11 -- ADDP2
JAPS TST1 TS1 OE10 AIS10 AISIE10 AISI10 -- ADDP1
JAE TST0 TS0 OE9 AIS9 AISIE9 AISI9 -- ADDP0
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-6. Secondary Register Set Bit Map
REGISTER
SRS LCS Not Used RPDE TPDE EZDE CVDEB Not Used ADDP
ADDRESS FOR LIUs 1-8
00 01 02 03 04 05 06 07-1E 1F
RW
RW RW RW RW RW RW RW RW
BIT 7
SRMS8 LCS8 -- RPDE8 TPDE8 EZDE8 CVDEB8 -- ADDP7
BIT 6
SRMS7 LCS7 -- RPDE7 TDPE7 EZDE7 CVDEB7 -- ADDP6
BIT 5
SRMS6 LCS6 -- RPDE6 TPDE6 EZDE6 CVDEB6 -- ADDP5
BIT 4
SRMS5 LCS5 -- RPDE5 TPDE5 EZDE5 CVDEB5 -- ADDP4
BIT 3
SRMS4 LSC4 -- RPDE4 TPDE4 EZDE4 CVDEB4 -- ADDP3
BIT 2
SRMS3 LCS3 -- RPDE3 TPDE3 EZDE3 CVDEB3 -- ADDP2
BIT 1
SRMS2 LSC2 -- RPDE2 TPDE2 EZDE2 CVDEB2 -- ADDP1
BIT 0
SRMS1 LSC1 -- RPDE1 TPDE1 EZDE1 CVDEB1 -- ADDP0
REGISTER
SRS LCS Not Used RPDE TPDE EZDE CVDEB Not Used ADDP
ADDRESS FOR LIUs 9-16
20 21 22 23 24 25 26 27-3E 3F
RW
RW RW RW RW RW RW RW -- RW
BIT 7
SRMS16 LCS16 -- RPDE16 TPDE16 EZDE16
CVDEB16
BIT 6
SRMS15 LCS15 -- RPDE15 TDPE15 EZDE15
CVDEB15
BIT 5
SRMS14 LCS14 -- RPDE14 TPDE14 EZDE14
CVDEB14
BIT 4
SRMS13 LCS13 -- RPDE13 TPDE13 EZDE13
CVDEB13
BIT 3
SRMS12 LSC12 -- RPDE12 TPDE12 EZDE12
CVDEB12
BIT 2
SRMS11 LCS11 -- RPDE11 TPDE11 EZDE11
CVDEB11
BIT 1
SRMS10 LSC10 -- RPDE10 TPDE10 EZDE10
CVDEB10
BIT 0
SRMS9 LSC9 -- RPDE9 TPDE9 EZDE9
CVDEB9
-- ADDP7
-- ADDP6
-- ADDP5
-- ADDP4
-- ADDP3
-- ADDP2
-- ADDP1
-- ADDP0
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-7. Individual LIU Register Set Bit Map
REGISTER
IJAE IJAPS IJAFDS IJAFLT ISCPD IAISEL MC RSMM1 RSMM2 RSMM3 RSMM4 RSL1 RSL2 RSL3 RSL4 BTCR BEIR LVDS RCLKI TCLKI CCR RDULR GISC ADDP
ADDRESS FOR LIUs 1-8
00 01 02 03 04 05 06 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 1E 1F
RW
RW RW RW R RW RW RW RW RW RW RW R R R R RW RW R RW RW RW RW RW RW
BIT 7
IJAE8 IJAPS8 IJAFDS8 IJAFLT8 ISCPD8 IAISEL8 PCLKI1 RTR2 RTR4 RTR6 RTR8 C2RSL3 C4RSL3 C6RSL3 C8RSL3 BTS2 BEIR8 LVDS8 RCLKI8 TCLKI8 PCLKS2 RDULR8 -- ADDP7
BIT 6
IJAE7 IJAPS7 IJAFDS7 IJAFLT7 ISCPD7 IAISEL7 PCLKI0 C2RSM2 C4RSM2 C6RSM2 C8RSM2 C2RSL2 C4RSL2 C6RSL2 C8RSL2 BTS1 BEIR7 LVDS7 RCLKI7 TCLKI7 PCLKS1 RDULR7 -- ADDP6
BIT 5
IJAE6 IJAPS6 IJAFDS6 IJAFLT6 ISCPD6 IAISEL6 TECLKE C2RSM1 C4RSM1 C6RSM1 C8RSM1 C2RSL1 C4RSL1 C6RSL1 C8RSL1 BTS0 BEIR6 LVDS6 RCLKI6 TCLKI6 PCLKS0 RDULR6 -- ADDP5
BIT 4
IJAE5 IJAPS5 IJAFDS5 IJAFLT5 ISCPD5 IAISEL5 CLKAE C2RSM0 C4RSM0 C6RSM0 C8RSM0 C2RSL0 C4RSL0 C6RSL0 C8RSL0 -- BEIR5 LVDS5 RCLKI5 TCLKI5 TECLKS RDULR5 -- ADDP4
BIT 3
IJAE4 IJAPS4 IJAFDS4 IJAFLT4 ISCPD4 IAISEL4 MPS1 RTR1 RTR3 RTR5 RTR7 C1RSL3 C3RSL3 C5RSL3 C7RSL3 -- BEIR4 LVDS4 RCLKI4 TCLKI4 CLKA3 RDULR4 -- ADDP3
BIT 2
IJAE3 IJAPS3 IJAFDS3 IJAFLT3 ISCPD3 IAISEL3 MPS0 C1RSM2 C3RSM2 C5RSM2 C7RSM2 C1RSL2 C3RSL2 C5RSL2 C7RSL2 -- BEIR3 LVDS3 RCLKI3 TCLKI3 CLKA2 RDULR3 -- ADDP2
BIT 1
IJAE2 IJAPS2 IJAFDS2 IJAFLT2 ISCPD2 IAISEL2 FREQS C1RSM1 C3RSM1 C5RSM1 C7RSM1 C1RSL1 C3RSL1 C5RSL1 C7RSL1 -- BEIR2 LVDS2 RCLKI2 TCLKI2 CLKA1 RDULR2 INTM ADDP1
BIT 0
IJAE1 IJAPS1 IJAFDS1 IJAFLT1 ISCPD1 IAISEL1 PLLE C1RSM0 C3RSM0 C5RSM0 C7RSM0 C1RSL0 C3RSL0 C5RSL0 C7RSL0 BERTE BEIR1 LVDS1 RCLKI1 TCLKI1 CLKA0 RDULR1 CWE ADDP0
REGISTER
IJAE IJAPS IJAFDS IJAFLT ISCPD IAISEL Not Used RSMM1 RSMM2 RSMM3 RSMM4 RSL1 RSL2 RSL3 RSL4 BTCR BEIR LVDS RCLKI TCLKI Not Used RDULR GISC ADDP
ADDRESS FOR LIUs 9-16
20 21 22 23 24 25 26 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 3E 3F
RW
RW RW RW R RW RW RW RW RW RW RW R R R R RW RW R RW RW RW RW RW RW
BIT 7
IJAE16 IJAPS16 IJAFDS16 IJAFLT16 ISCPD16 IAISEL16 -- RTR10 RTR12 RTR14 RTR8 C10RSL3 C12RSL3 C14RSL3 C16RSL3 BTS2 BEIR16 LVDS16 RCLKI16 TCLKI16 -- RDULR16 -- ADDP7
BIT 6
IJAE15 IJAPS15 IJAFDS15 IJAFLT15 ISCPD15 IAISEL15 -- C10RSM2 C12RSM2 C14RSM2 C16RSM2 C10RSL2 C12RSL2 C14RSL2 C16RSL2 BTS1 BEIR15 LVDS15 RCLKI15 TCLKI15 -- RDULR15 -- ADDP6
BIT 5
IJAE14 IJAPS14 IJAFDS14 IJAFLT14 ISCPD14 IAISEL14 -- C10RSM1 C12RSM1 C14RSM1 C16RSM1 C10RSL1 C12RSL1 C14RSL1 C16RSL1 BTS0 BEIR14 LVDS14 RCLKI14 TCLKI14 -- RDULR14 -- ADDP5
BIT 4
IJAE13 IJAPS13 IJAFDS13 IJAFLT13 ISCPD13 IAISEL13 -- C10RSM0 C12RSM0 C14RSM0 C16RSM0 C10RSL0 C12RSL0 C14RSL0 C16RSL0 -- BEIR13 LVDS13 RCLKI13 TCLKI13 -- RDULR13 -- ADDP4
BIT 3
IJAE12 IJAPS12 IJAFDS12 IJAFLT12 ISCPD12 IAISEL12 -- RTR9 RTR11 RTR13 RTR16 C9RSL3 C11RSL3 C13RSL3 C15RSL3 -- BEIR12 LVDS12 RCLKI12 TCLKI12 -- RDULR12 -- ADDP3
BIT 2
IJAE11 IJAPS11 IJAFDS11 IJAFLT11 ISCPD11 IAISEL11 -- C9RSM2 C11RSM2 C13RSM2 C16RSM2 C9RSL2 C11RSL2 C13RSL2 C15RSL2 -- BEIR11 LVDS11 RCLKI11 TCLKI11 -- RDULR11 -- ADDP2
BIT 1
IJAE10 IJAPS10 IJAFDS10 IJAFLT10 ISCPD10 IAISEL10 -- C9RSM1 C11RSM1 C13RSM1 C16RSM1 C9RSL1 C11RSL1 C13RSL1 C15RSL1 -- BEIR10 LVDS10 RCLKI10 TCLKI10 -- RDULR10 INTM ADDP1
BIT 0
IJAE9 IJAPS9 IJAFDS9 IJAFLT9 ISCPD9 IAISEL9 -- C9RSM0
C11RSM0 C13RSM0 C16RSM0
C9RSL0 C11RSL0 C13RSL0 C15RSL0 BERTE BEIR9 LVDS9 RCLKI9 TCLKI9 -- RDULR9 CWE ADDP0
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-8. BERT Register Bit Map
REG BCR Not Used BPCR1 BPCR2 BSPR1 BSPR2 BSPR3 BSPR4 TEICR Not Used BSR Not Used BSRL Not Used BSRIE Not Used RBECR1 RBECR2 RBECR3 Not Used RBCR1 RBCR2 RBCR3 RBCR4 Not Used ADDP ADDRESS FOR LIUs 1-8 00 01 02 03 04 05 06 07 08 09-0B 0C 0D 0E 0F 10 11-13 14 15 16 17 18 19 1A 1B 1C-1E 1F ADDRESS FOR LIUs 9-16 20 21 22 23 24 25 26 27 28 29-2B 2C 2D 2E 2F 30 31-33 34 35 36 37 38 39 3A 3B 3C-3E 3F RW RW -- RW -- RW RW -- RW -- R/W RL/W -- RW -- R R R -- R R R R -- RW BIT 7 PMUM -- -- -- BSP7 BSP15 BSP23 BSP31 -- -- -- -- -- -- -- -- BEC7 BEC15 BEC23 -- BC7 BC15 BC23 BC31 -- ADDP7 BIT 6 LPMU -- QRSS -- BSP6 BSP14 BSP22 BSP30 -- -- -- -- -- -- -- -- BEC6 BEC14 BEC22 -- BC6 BC14 BC22 BC30 -- ADDP6 BIT 5 RNPL -- PTS -- BSP5 BSP13 BSP21 BSP29 TEIR2 -- -- -- -- -- -- -- BEC5 BEC13 BEC21 -- BC5 BC13 BC21 BC29 -- ADDP5 BIT 4 RPIC -- PLF4 PTF4 BSP4 BSP12 BSP20 BSP28 TEIR1 -- -- -- -- -- -- -- BEC4 BEC12 BEC20 -- BC4 BC12 BC20 BC28 -- ADDP4 BIT 3 MPR -- PLF3 PTF3 BSP3 BSP11 BSP19 BSP27 TEIR0 -- PMS -- PMSL -- PMSIE -- BEC3 BEC11 BEC19 -- BC3 BC11 BC19 BC27 -- ADDP3 BIT 2 APRD -- PLF2 PTF2 BSP2 BSP10 BSP18 BSP26 BEI -- -- -- BEL -- BEIE -- BEC2 BEC10 BEC18 -- BC2 BC10 BC18 BC26 -- ADDP2 BIT 1 TNPL -- PLF1 PTF1 BSP1 BSP9 BSP17 BSP25 TSEI -- BEC -- BECL -- BECIE -- BEC1 BEC9 BEC17 -- BC1 BC9 BC17 BC25 -- ADDP1 BIT 0 TPIC -- PLF0 PTF0 BSP0 BSP8 BSP16 BSP24 MEIMS -- OOS -- OOSL -- OOSIE -- BEC0 BEC8 BEC16 -- BC0 BC8 BC16 BC24 -- ADDP0
Note: Underlined bits are read only.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
6.1
Register Description
This sections details the register description(s) of each bit. Whenever the variable "n" in italics is used in any of the register descriptions, it represents 1-16. Note that in the register descriptions, there are duplicate registers for LIUs 1-8 and LIUs 9-16. There are registers in LIUs 1-8 that do not have a duplicate in the register set for LIUs 9-16. For these registers, only one address is listed. All other registers list two addresses, one for LIUs 1-8 and one for LIUs 9-16.
6.1.1
Primary Register Bank
The ADDP register must be set to 00h to access this bank. Register Name: Register Description: Register Address: Bit # Name 7 ID7 6 ID6 ID ID Register 00h 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0
Bits 7: Device CODE ID Bit 7 (ID7). This bit is `zero' for short-haul operation. Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device contains. Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID2 to ID0). These bits tell the user the revision of the part. Contact the factory for details.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 ALBC8 0 6 ALBC7 0
ALBC Analog Loopback Control 01h 5 ALBC6 0 21h 5 ALBC14 0 4 ALBC13 0 3 ALBC12 0 2 ALBC11 0 1 ALBC10 0 0 ALBC9 0 4 ALBC5 0 3 ALBC4 0 2 ALBC3 0 1 ALBC2 0 0 ALBC1 0
Register Address (LIUs 9-16): Bit # Name Default 7 ALBC16 0
6 ALBC15 0
Bit 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in Analog Loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. LOS Detector is still in operation. The jitter attenuator is in use if enabled for the Transmitter or Receiver.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RLBC8 0 6 RLBC7 0 22h 5 RLBC14 0 4 RLBC13 0 3 RLBC12 0 2 RLBC11 0 1 RLBC10 0 0 RLBC9 0 RLBC Remote Loopback Control 02h 5 RLBC6 0 4 RLBC5 0 3 RLBC4 0 2 RLBC3 0 1 RLBC2 0 0 RLBC1 0
Register Address (LIUs 9-16): Bit # Name Default 7 RLBC16 0
6 RLBC15 0
Bit 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, Remote Loopback is enabled on LIUn. The Analog Received Signal goes through the Receive Digital and is looped back to the Transmitter. The data at TPOS and TNEG is ignored. The jitter attenuator is in use if enabled.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 TAOE8 0 6 TAOE7 0
TAOE Transmit All Ones Enable 03h 5 TAOE6 0 23h 5 TAOE14 0 4 TAOE13 0 3 TAOE12 0 2 TAOE11 0 1 TAOE10 0 0 TAOE9 0 4 TAOE5 0 3 TAOE4 0 2 TAOE3 0 1 TAOE2 0 0 TAOE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 TAOE16 0 6
TAOE15 0
Bit 7 to 0: Transmit All Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of All ones on TTIP and TRING are sent on Channel n. MCLK is used as a reference clock for Transmit All Ones Signal. The data arriving at TPOS and TNEG is ignored.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LOS8 0 6 LOS7 0
LOSS Loss of Signal Status 04h 5 LOS6 0 24h 5 LOS14 0 4 LOS13 0 3 LOS12 0 2 LOS11 0 1 LOS10 0 0 LOS9 0 4 LOS5 0 3 LOS4 0 2 LOS3 0 1 LOS2 0 0 LOS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 LOS16 0 6 LOS15 0
Bit 7 to 0: Loss of Signal Status Channel n (LOSn). When this bit is set, a LOS condition has been detected on LIUn. The criteria and conditions of LOS are described in Loss of Signal.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 DFMS8 0 6 DFMS7 0
DFMS Driver Fault Monitor Status 05h 5 DFMS6 0 25h 5 DFMS14 0 4 DFMS13 0 3 DFMS12 0 2 DFMS11 0 1 DFMS10 0 0 DFMS9 0 4 DFMS5 0 3 DFMS4 0 2 DFMS3 0 1 DFMS2 0 0 DFMS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 DFMS16 0
6 DFMS15 0
Bit 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short or open circuit at the Transmit Driver for LIUn.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LOSIE8 0 6 LOSIE7 0
LOSIE Loss of Signal Interrupt Enable 06h 5 LOSIE6 0 26h 5 LOSIE14 0 4 LOSIE13 0 3 LOSIE12 0 2 LOSIE11 0 1 LOSIE10 0 0 LOSIE9 0 4 LOSIE5 0 3 LOSIE4 0 2 LOSIE3 0 1 LOSIE2 0 0 LOSIE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 LOSIE16 0
6 LOSIE15 0
Bit 7 to 0: Loss of Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in LOS Status for LIUn can generate an Interrupt.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 DFMIE8 0
DFMIE Driver Fault Monitor Interrupt Enable 07h 5 DFMIE6 0 4 DFMIE5 0 3 DFMIE4 0 2 DFMIE3 0 1 DFMIE2 0 0 DFMIE1 0
6 DFMIE7 0 27h
Register Address (LIUs 9-16): Bit # Name Default 7 DFMIE16 0
6 DFMIE15 0
5 DFMIE14 0
4 DFMIE13 0
3 DFMIE12 0
2 DFMIE11 0
1 DFMIE10 0
0 DFMIE9 0
Bit 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM Status can generate an Interrupt in Monitor n.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LOSIS8 0 6 LOSIS7 0
LOSIS Loss of Signal Interrupt Status 08h 5 LOSIS6 0 28h 5 LOSIS14 0 4 LOSIS13 0 3 LOSIS12 0 2 LOSIS11 0 1 LOSIS10 0 0 LOSIS9 0 4 LOSIS5 0 3 LOSIS4 0 2 LOSIS3 0 1 LOSIS2 0 0 LOSIS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 LOSIS16 0
6 LOSIS15 0
Bit 7 to 0: Loss of Signal Interrupt Status Channel n (LOSISn). When this bit is set, it indicates a LOS status has transition from a "0 to 1" or "1 to 0" and was detected for LIUn. The bit for LIUn is enabled by register LOSIE(06h). This bit when latched is cleared on a read operation.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 DFMIS8 0
DFMIS Driver Fault Monitor Interrupt Status 09h 5 DFMIS6 0 4 DFMIS5 0 3 DFMIS4 0 2 DFMIS3 0 1 DFMIS2 0 0 DFMIS1 0
6 DFMIS7 0 29h
Register Address (LIUs 9-16): Bit # Name Default 7 DFMIS16 0
6 DFMIS15 0
5 DFMIS14 0
4 DFMIS13 0
3 DFMIS12 0
2 DFMIS11 0
1 DFMIS10 0
0 DFMIS9 0
Bit 7 to 0: Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has transitioned from "0 to 1" or "1 to 0" and was detected for LIUn. The bit for LIUn is enabled by register DFMIE(07h). This bit when latched is cleared on a read operation.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 SWRL 0 6 SWRL 0
SWR Software Reset 0Ah 5 SWRL 0 4 SWRL 0 3 SWRL 0 2 SWRL 0 1 SWRL 0 0 SWRL 0
Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be generated that resets the lower set of registers (LIUs 1-8). All the registers will be restored to their default values. A read operation will always read back all zeros.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Address (LIUs 9-16): Bit # Name Default 7 SWRU 0 6 SWRU 0 2Ah 5 SWRU 0 4 SWRU 0 3 SWRU 0 2 SWRU 0 1 SWRU 0 0 SWRU 0
Bit 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least 1 us reset will be generated that resets the upper set of registers (LIUs 9-16). All the registers will be restored to their default values. A read operation will always read back all zeros.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 -0 6 -0
GMC G.772 Monitoring Control 0Bh 5 -0 4 -0 3 GMC3 0 2 GMC2 0 1 GMC1 0 0 GMC0 0
Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive monitoring. Receiver 1 is used to monitor channels 2 to 8 of one receiver from RTIP2-8/RRING2-8 or of one transmitter from TTIP2-8/TRING2-8. See Table 6-9. Register Address (LIUs 9-16): Bit # Name Default 7 -0 6 -0 2Bh 5 -0 4 -0 3 GMC3 0 2 GMC2 0 1 GMC1 0 0 GMC0 0
Bit 7 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for nonintrusive monitoring. Receiver 9 is used to monitor channels 10 to 16 of one receiver from RTIP10-16/RRING10-16 or of one transmitter from TTIP10-16/TRING10-16. See Table 6-10
Table 6-9. G.772 Monitoring Control (LIU 1)
GMC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GMC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GMC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GMC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SELECTION No Monitoring Receiver 2 Receiver 3 Receiver 4 Receiver 5 Receiver 6 Receiver 7 Receiver 8 No Monitoring Transmitter 2 Transmitter 3 Transmitter 4 Transmitter 5 Transmitter 6 Transmitter 7 Transmitter 8
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-10. G.772 Monitoring Control (LIU 9)
GMC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GMC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GMC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GMC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SELECTION No Monitoring Receiver 10 Receiver 11 Receiver 12 Receiver 13 Receiver 14 Receiver 15 Receiver 16 No Monitoring Transmitter 10 Transmitter 11 Transmitter 12 Transmitter 13 Transmitter 14 Transmitter 15 Transmitter 16
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 DLBC8 0 6 DLBC7 0
DLBC Digital Loopback Control 0Ch 5 DLBC6 0 2Ch 5 DLBC14 0 4 DLBC13 0 3 DLBC12 0 2 DLBC11 0 1 DLBC10 0 0 DLBC9 0 4 DLBC5 0 3 DLBC4 0 2 DLBC3 0 1 DLBC2 0 0 DLBC1 0
Register Address (LIUs 9-16): Bit # Name Default 7 DLBC16 0
6 DLBC15 0
Bit 7 to 0: Digital Loopback Control Channel n (DLBCn). When this bit is set the LIUn is placed in Digital Loopback. The data at TPOS/TNEG is encoded and looped back to the decoder and output on RPOS/RNEG. The Jitter Attenuator can optionally be included in the Transmit or Receive Paths.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LASCS8 0 LASCS LOS/AIS Criteria Selection 0Dh 5 LASCS6 0 4 LASCS5 0 3 LASCS4 0 2 LASCS3 0 1 LASCS2 0 0 LASCS1 0
6 LASCS7 0 2Dh
Register Address (LIUs 9-16): Bit # Name Default 7 LASCS16 0
6 LASCS15 0
5 LASCS14 0
4 LASCS13 0
3 LASCS12 0
2 LASCS11 0
1 LASCS10 0
0 LASCS9 0
Bit 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). This bit is used for LOS/AIS Selection Criteria for LIUn. In E1 mode if set it uses ETSI (300233) mode selections. If reset it uses G.775 criteria. In T1/J1 mode T1.231 criteria is selected.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 ATAOS8 0
ATAOS Automatic Transmit All Ones Select 0Eh 5 ATAOS6 0 4 ATAOS5 0 3 ATAOS4 0 2 ATAOS3 0 1 ATAOS2 0 0 ATAOS1 0
6 ATAOS7 0 2Eh
Register Address (LIUs 9-16): Bit # Name Default 7 ATAOS16 0
6 ATAOS15 0
5 ATAOS14 0
4 ATAOS13 0
3 ATAOS12 0
2 ATAOS11 0
1 ATAOS10 0
0 ATAOS9 0
Bit 7 to 0: Automatic Transmit All Ones Select Channel n (ATAOSn). When this bit is set All Ones Signal is sent if a Loss of Signal is detected for LIUn. "All Ones Signal" uses MCLK as the reference clock.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7
-
GC Global Configuration 0Fh 5 SCPD 0 4 CODE 0 3 JADS 0 2 RTCTL 0 1 JAPS 0 0 JAE 0
0
6 AISEL 0
RTCTL controls all 16 LIUs. All other bits are for LIUs 1-8 only. Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting LOS for each channel. The individual LIU Register IAISEL settings will be ignored when this bit is set. When reset, the IAISEL register will have control. Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the transmitters. The individual LIU Register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD register will have control.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Bit 4: Code. If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored when this bit is set. If reset, the LCS register will have control. Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control. Bit 2: Receive Termination Control (RTCTL). If this bit is set the OE pin has been granted control over all the internal termination of all the LIU Receivers. Otherwise, see the RIMPON bit. Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA will be in the Receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU by settings in Register IJAPS. Note that when bit JAE is set, the settings in Register IJAPS will be ignored. Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the IJAE register will be ignored if this register is set. If reset, the IJAE register will have control. Register Address (LIUs 9-16): Bit # Name Default 7 0 6 AISEL 0 2Fh 5 SCPD 0 4 CODE 0 3 JADS 0 2 0 1 JAPS 0 0 JAE 0
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the System Side upon detecting LOS for each channel. The individual LIU Register IAISEL settings will be ignored when this bit is set. When reset, the IAISEL register will have control. Bit 5: Short Circuit Protection Disable (SCPD). If this bit is set the Short Circuit protection is disabled for all the transmitters. The individual LIU Register ISCPD settings will be ignored when this bit is set. When reset, the ISCPD register will have control. Bit 4: Code. If this bit is set AMI encoder/decoder is selected. The LCS register settings will be ignored when this bit is set. If reset, the LCS register will have control. Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The settings in the IJAFDS register will be ignored if this register is set. If reset the IJAFDS register will have control. Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA will be in the Receive path and when default or set low in the Transmit path. These settings can be changed for an individual LIU by settings in Register IJAPS. Note that when bit JAE is set, the settings in Register IJAPS will be ignored. Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the IJAE register will be ignored if this register is set. If reset, the IJAE register will have control.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 -0 6 -0
TST Template Select Transmitter Register 10h 5 -0 4 -0 3 -0 2 TST2 0 1 TST1 0 0 TST0 0
Bit 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the Transceiver that the Transmit Template Select Register (hex 11) applies to for LIUs 1-8. See .
Register Address (LIUs 9-16): Bit # Name Default 7 -0 6 -0
30h 5 -0 4 -0 3 -0 2 TST2 0 1 TST1 0 0 TST0 0
Bit 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the Transceiver that the Transmit Template Select Register (hex 11) applies to LIUs 9-16. See Table 6-13.
Table 6-12. TST Template Select Transmitter Register
TST[2:0] 000 001 010 011 CHANNEL 1 2 3 4 TST[2:0] 100 101 110 111 CHANNEL 5 6 7 8
Table 6-13. TST Template Select Transmitter Register
TST[2:0] 000 001 010 011 CHANNEL 9 10 11 12 TST[2:0] 100 101 110 111 CHANNEL 13 14 15 16
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 RIMPON 0 TS Template Select Register 11h 31h 5 -- 0 4 -- 0 3 TIMPRM 0 2 TS2 0 1 TS1 0 0 TS0 0
6 TIMPOFF 0
Bit 7: Receive Impedance Match On (RIMPON). If this bit is set Receive Impedance matching is turned ON. Otherwise the receiver is in High Z. Note that the OE pin can have control instead of this bit when the GC.RTCTL bit is set. Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set all the internal Transmit Terminating Impedance is turned Off. Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal Transmit Termination impedance and Receive Impedance Match for E1 mode and T1/J1 mode. 0 = 75W for E1 mode or 100W for T1 mode. 1 = 120W for E1 mode or 110W for J1 mode. Bit 2 to 0: Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the Template, and the settings for various cable lengths. The impedance Termination for the Transmitter and Impedance Match for the Receiver are specified by bit TIMPRM. See Table 6-14 for bit selection of TS[2:0].
Table 6-14. Template Selection
TS[2:0] 011 100 101 110 111 000 001 and 010 TEMPLATE SELECTION LINE LENGTH CABLE LOSS (ft) (dB) 0-133 ABAM 0.6 133-266 ABAM 1.2 266-399 ABAM 1.8 399-533 ABAM 2.4 533-655 ABAM 3.0 G.703 Coaxial & Twisted pair cable Reserved -- OE Output Enable 12h 5 OE6 0 32h 5 OE14 0 4 OE13 0 3 OE12 0 2 OE11 0 1 OE10 0 0 OE9 0 4 OE5 0 3 OE4 0 2 OE3 0 1 OE2 0 0 OE1 0 IMPEDANCE (W) 100/110 100/110 100/110 100/110 100/110 75/120 --
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 OE8 0 6 OE7 0
Register Address (LIUs 9-16): Bit # Name Default 7 OE16 0 6 OE15 0
Bit 7 to 0: Output Enable Channel n (OEn). When this bit is in default the Transmitter output for LIUn is in High-Z. When this bit is set the Transmitter output for LIUn is enabled. Note that the OE pin will override this setting when low. 57 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 AIS8 0 6 AIS7 0
AIS Alarm Indication Signal Status 13h 5 AIS6 0 33h 5 AIS14 0 4 AIS13 0 3 AIS12 0 2 AIS11 0 1 AIS10 0 0 AIS9 0 4 AIS5 0 3 AIS4 0 2 AIS3 0 1 AIS2 0 0 AIS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 AIS16 0 6 AIS15 0
Bit 7 to 0: Alarm Indication Signal Channel n (AISn). This bit will be set when AIS is detected for LIUn. The criteria for AIS selection is detailed in the AIS Section. The selection of the AIS criteria is done by settings in LASCS (0D) Register.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 AISIE8 0 6 AISIE7 0
AISIE AIS Interrupt Enable 14h 5 AISIE6 0 34h 5 AISIE14 0 4 AISIE13 0 3 AISIE12 0 2 AISIE11 0 1 AISIE10 0 0 AISIE9 0 4 AISIE5 0 3 AISIE4 0 2 AISIE3 0 1 AISIE2 0 0 AISIE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 AISIE16 0
6 AISIE15 0
Bit 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set interrupts can be generated for LIUn if AIS Status transitions.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 AISI8 0 6 AISI7 0 35h 5 AISI14 0 4 AISI13 0 3 AISI12 0 2 AISI11 0 1 AISI10 0 0 AISI9 0 AISI AIS Interrupt 15h 5 AISI6 0 4 AISI5 0 3 AISI4 0 2 AISI3 0 1 AISI2 0 0 AISI1 0
Register Address (LIUs 9-16): Bit # Name Default 7 AISI16 0 6 AISI15 0
Bit 7 to 0: AIS Interrupt Channel n (AISIn). This bit is set when AIS Transitions from a "0 to 1" or "1 to 0" and Interrupts are enabled by AISIE(14) register for LIUn. This bit if set, is cleared on a read operation or when the interrupt enable register is disabled.
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 ADDP7 0 6 ADDP6 0
ADDP Address Pointer 1Fh 3Fh 5 ADDP5 0 4 ADDP4 0 3 ADDP3 0 2 ADDP2 0 1 ADDP1 0 0 ADDP0 0
Bit 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the Primary Registers, the Secondary Registers, Individual Registers, and BERT Registers. See Table 6-15 for bank selection. The register space contains control for channels 1 to 8 from address 00 hex to 1F hex and a duplicate set of registers for control of channels 9 to 16 from address 20 hex to 3F hex. The ADDP at address 1F hex select the banks for the set of registers for LIUs 1-8. The ADDP register at address 3F select the banks for the set of registers for LIUs 9-16.
Table 6-15. Address Pointer Bank Selection
ADDP7-ADDP0 (HEX) 00 AA 01 02 BANK NAME Primary Bank Secondary Bank Individual LIU Bank BERT Bank
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
6.1.2
Secondary Register Bank
The ADDP register must be set to AAh in order to access this bank. Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 SRMS8 0 6 SRMS7 0 20h 5 SRMS14 0 4 SRMS13 0 3 SRMS12 0 2 SRMS11 0 1 SRMS10 0 0 SRMS9 0 SRMS Single-Rail Mode Select 00h 5 SRMS6 0 4 SRMS5 0 3 SRMS4 0 2 SRMS3 0 1 SRMS2 0 0 SRMS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 SRMS16 0
6 SRMS15 0
Bit 7 to 0: Single-Rail Mode Select Channel n (SRMSn). When this bit is set single-rail mode is selected for the System Transmit and Receive n. If this bit is reset dual rail is selected.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LCS8 0 6 LCS7 0
LCS Line Code Selection 01h 5 LCS6 0 21h 5 LCS14 0 4 LCS13 0 3 LCS12 0 2 LCS11 0 1 LCS10 0 0 LCS9 0 4 LCS5 0 3 LCS4 0 2 LCS3 0 1 LCS2 0 0 LCS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 LCS16 0 6 LCS15 0
Bit 7 to 0: Line Code Select Channel n (LCSn). When this bit is set AMI encoding/decoding is selected for LIUn. If reset B8ZS or HDB3 encoding/decoding is selected for LIUn. Note that if the GC.CODE register bit is set it will ignore this register.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RPDE8 0 6 RPDE7 0 23h 5 RPDE14 0 4 RPDE13 0 3 RPDE12 0 2 RPDE11 0 1 RPDE10 0 0 RPDE9 0 RPDE Receive Power-Down Enable 03h 5 RPDE6 0 4 RPDE5 0 3 RPDE4 0 2 RPDE3 0 1 RPDE2 0 0 RPDE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 RPDE16 0
6 RPDE15 0
Bit 7 to 0: Receive Power-Down Enable Channel n (RPDEn). When this bit is set the Receiver for LIUn is powered down.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 TPDE8 0 6 TPDE7 0
TPDE Transmit Power-Down Enable 04h 5 TPDE6 0 24h 5 TPDE14 0 4 TPDE13 0 3 TPDE12 0 2 TPDE11 0 1 TPDE10 0 0 TPDE9 0 4 TPDE5 0 3 TPDE4 0 2 TPDE3 0 1 TPDE2 0 0 TPDE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 TPDE16 0
6 TPDE15 0
Bit 7 to 0: Transmit Power-Down Enable Channel n(TPDEn). When this bit is set the Transmitter for LIUn is powered down.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 EXZDE8 0
EZDE Excessive Zero Detect Enable 05h 5 EXZDE6 0 4 EXZDE5 0 3 EXZDE4 0 2 EXZDE3 0 1 EXZDE2 0 0 EXZDE1 0
6 EXZDE7 0 25h
Register Address (LIUs 9-16): Bit # Name Default 7 EXZDE16 0
6 EXZDE15 0
5 EXZDE14 0
4 EXZDE13 0
3 EXZDE12 0
2 EXZDE11 0
1 EXZDE10 0
0 EXZDE9 0
Bit 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset Excessive Zero detection is disabled for LIUn. When this bit is set Excessive Zero Detect Enable is enabled. Excessive Zero Detection is only relevant in single-rail mode with HDB3 or B8ZS encoding.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 CVDEB8 0
CVDEB Code Violation Detect Enable Bar 06h 5 CVDEB6 0 4 CVDEB5 0 3 CVDEB4 0 2 CVDEB3 0 1 CVDEB2 0 0 CVDEB1 0
6 CVDEB7 0 26h
Register Address (LIUs 9-16): Bit # Name Default 7 CVDEB16 0
6 CVDEB15 0
5 CVDEB14 0
4 CVDEB13 0
3 CVDEB12 0
2 CVDEB11 0
1 CVDEB10 0
0 CVDEB9 0
Bit 7 to 0: Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only relevant in single-rail mode with HDB3 encoding.
6.1.3
Individual LIU Register Bank
The ADDP register must be set to 01h to access this bank. Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 IJAE8 0 6 IJAE7 0 20h 5 IJAE14 0 4 IJAE13 0 3 IJAE12 0 2 IJAE11 0 1 IJAE10 0 0 IJAE9 0 IJAE Individual Jitter Attenuator Enable 00h 5 IJAE6 0 4 IJAE5 0 3 IJAE4 0 2 IJAE3 0 1 IJAE2 0 0 IJAE1 0
Register Address (LIUs 9-16): Bit # Name Default 7 IJAE16 0 6 IJAE15 0
Bit 7-0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIU Jitter Attenuator n is Enabled. Note that if the GC.JAE register bit is set this register will be ignored.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 IJAPS8 0 6 IJAPS7 0
IJAPS Individual Jitter Attenuator Position Select 01h 5 IJAPS6 0 21h 5 IJAPS14 0 4 IJAPS13 0 3 IJAPS12 0 2 IJAPS11 0 1 IJAPS10 0 0 IJAPS9 0 4 IJAPS5 0 3 IJAPS4 0 2 IJAPS3 0 1 IJAPS2 0 0 IJAPS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 IJAPS16 0
6 IJAPS15 0
Bit 7-0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high the JA is in the Receive path n, and when this bit is default or set low then the JA is in the Transmit path n. Note that if the GC.JAE register bit is set, this register will be ignored.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 IJAFDS8 0
IJAFDS Individual Jitter Attenuator Fifo Depth Select 02h 5 IJAFDS6 0 4 IJAFDS5 0 3 IJAFDS4 0 2 IJAFDS3 0 1 IJAFDS2 0 0 IJAFDS1 0
6 IJAFDS7 0 22h
Register Address (LIUs 9-16): Bit # Name Default 7 IJAFDS16 0
6 IJAFDS15 0
5 IJAFDS14 0
4 IJAFDS13 0
3 IJAFDS12 0
2 IJAFDS11 0
1 IJAFDS10 0
0 IJAFDS9 0
Bit 7-0: Individual Jitter Attenuator Fifo Depth Select n (IJAFDSn). When this bit is set for LIUn the JA Fifo depth will be 128 bits. When reset the JA FIFO depth will be 32 bits. Note that if the GC.IJAFDS register bit is set this register will be ignored.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 IJAFLT8 0
IJAFLT Individual Jitter Attenuator FIFO Limit Trip 03h 5 IJAFLT6 0 4 IJAFLT5 0 3 IJAFLT4 0 2 IJAFLT3 0 1 IJAFLT2 0 0 IJAFLT1 0
6 IJAFLT7 0 23h
Register Address (LIUs 9-16): Bit # Name Default 7 IJAFLT16 0
6 IJAFLT15 0
5 IJAFLT14 0
4 IJAFLT13 0
3 IJAFLT12 0
2 IJAFLT11 0
1 IJAFLT10 0
0 IJAFLT9 0
Bit 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit for Transmitter n. This bit will be cleared when read. 63 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 ISCPD8 0
ISCPD Individual Short Circuit Protection Disabled 04h 5 ISCPD6 0 4 ISCPD5 0 3 ISCPD4 0 2 ISCPD3 0 1 ISCPD2 0 0 ISCPD1 0
6 ISCPD7 0 24h
Register Address (LIUs 9-16): Bit # Name Default 7 ISCPD16 0
6 ISCPD15 0
5 ISCPD14 0
4 ISCPD13 0
3 ISCPD12 0
2 ISCPD11 0
1 ISCPD10 0
0 ISCPD9 0
Bit 7-0: Individual Short Circuit Protection Disable n. (ISCPDn). When this bit is set the Short Circuit protection is disabled for the individual Transmitter n. Note that if the GC.SCPD register bit is set, the settings in this register will be ignored.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 IAISEL8 0
IAISEL Individual AIS Select 05h 5 IAISEL6 0 4 IAISEL5 0 3 IAISEL4 0 2 IAISEL3 0 1 IAISEL2 0 0 IAISEL1 0
6 IAISEL7 0 25h
Register Address (LIUs 9-16): Bit # Name Default 7 IAISEL16 0
6 IAISEL15 0
5 IAISEL14 0
4 IAISEL13 0
3 IAISEL12 0
2 IAISEL11 0
1 IAISEL10 0
0 IAISEL9 0
Bit 7-0: Individual AIS Enable During Loss n (IAISELn). When this bit is set Individual AIS Enable During loss is enabled for the individual Receiver n and AIS is sent to the system side upon detection a LOS of signal. Note that if the GC.AISEL register bit is set, the settings in this register will be ignored.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address: Bit # Name Default 7 PCLKI1 0 6 PCLKI0 0
MC Master Clock Select 06h 5 TECLKE 0 4 CLKAE 0 3 MPS1 0 2 MPS0 0 1 FREQS 0 0 PLLE 0
Bit 7 to 6: PLL Clock Input [1:0] (PCLKI[1:0]). These bits select the input into to the PLL. 00 MCLK is used. 01 RCLK1 to 8 is used based on the selection in register CCR. 10 RCLK9 to 16 is used based on the selection in register CCR. 11 Reserved. Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK will be disabled and the TECLK output is a LOS output. TECLK requires PLLE to be set for correct functionality. Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set CLKA will be disabled and the CLKA output is a LOS output. CLKA requires PLLE to be set for correct functionality. Bit 3 to 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK frequency for the DS26324. See Table 6-16 for details. This register when written to will also controller functionality of channels 9 to 16. Bit 1: Frequency Select(FREQS). In conjunction with MPS[1:0] selects the external MCLK frequency for the DS26324. If this bit is set the external Master clock can be 1.544 MHz or multiple thereof. If not set the external master clock can be 2.048 MHz or multiple thereof. See Table 6-16 for details. This register when written to will also controller functionality of channels 9 to 16. Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If not set MCLK will be the applied input clock.
Table 6-16. MCLK Selections for the DS26324
PLLE 0 0 1 1 1 1 1 1 1 1 MPS1, MPS0 xx xx 00 01 10 11 00 01 10 11 MCLK MHz, 50ppm 1.544 2.048 1.544 3.088 6.176 12.352 2.048 4.096 8.192 16.384 FREQS x x 1 1 1 1 0 0 0 0 T1 OR E1 MODE T1 E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1 T1/J1 or E1
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RTR2 0 RSMM1 Receive Sensitivity Monitor Mode 1 08h 5 C2RSM1 0 4 C2RSM0 0 3 RTR1 0 2 C1RSM2 0 1 C1RSM1 0 0 C1RSM0 0
6 C2RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 2(RTR2). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6 - 4: Channel 2 Receive Sensitivity/Monitor Select [2:0] (C2RSM[2:0]). When bits C2RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 1(RTR1). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2 - 0: Channel 1 Receive Sensitivity/Monitor Select [2:0] (C1RSM[2:0]). When bits C1RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Register Address (LIUs 9-16): Bit # Name Default 7 RTR10 0 28h 5 C10RSM1 0 4 C10RSM0 0 3 RTR9 0 2 C9RSM2 0 1 C9RSM1 0 0 C9RSM0 0
6 C10RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 10(RTR10). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 10 Receive Sensitivity/Monitor Select [2:0] (C10RSM[2:0]). When bits C10RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 9(RTR9). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 9 Receive Sensitivity/Monitor Select [2:0] (C9RSM[2:0]). When bits C9RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RTR4 0
RSMM2 Receive Sensitivity Monitor Mode 2 09h 5 C4RSM1 0 4 C4RSM0 0 3 RTR3 0 2 C3RSM2 0 1 C3RSM1 0 0 C3RSM0 0
6 C4RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 4(RTR4). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 4 Receive Sensitivity/Monitor Select [2:0] (C4RSM[2:0]). When bits C4RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 3(RTR3). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 3 Receive Sensitivity/Monitor Select [2:0] (C3RSM[2:0]). When bits C3RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Register Address (LIUs 9-16): Bit # Name Default 7 RTR12 0 29h 5 C12RSM1 0 4 C12RSM0 0 3 RTR11 0 2 C11RSM2 0 1 C11RSM1 0 0 C11RSM0 0
6 C12RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 12(RTR12). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 12 Receive Sensitivity/Monitor Select [2:0] (C12RSM[2:0]). When bits C12RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 11(RTR11). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 11 Receive Sensitivity/Monitor Select [2:0] (C11RSM[2:0]). When bits C11RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RTR6 0
RSMM3 Receive Sensitivity Monitor Mode 3 0Ah 5 C6RSM1 0 4 C6RSM0 0 3 RTR5 0 2 C5RSM2 0 1 C5RSM1 0 0 C5RSM0 0
6 C6RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 6(RTR6). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 6 Receive Sensitivity/Monitor Select [2:0] (C6RSM[2:0]). When bits C6RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 5(RTR5). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 5 Receive Sensitivity/Monitor Select [2:0] (C5RSM[2:0]). When bits C5RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Register Address (LIUs 9-16): Bit # Name Default 7 RTR14 0 2Ah 5 C14RSM1 0 4 C14RSM0 0 3 RTR13 0 2 C13RSM2 0 1 C13RSM1 0 0 C13RSM0 0
6 C14RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 14(RTR14). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 14 Receive Sensitivity/Monitor Select [2:0] (C14RSM[2:0]). When bits C14RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 13(RTR13). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 13 Receive Sensitivity/Monitor Select [2:0] (C13RSM[2:0]). When bits C13RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RTR8 0
RSMM4 Receive Sensitivity Monitor Mode 4 0Bh 5 C8RSM1 0 4 C8RSM0 0 3 RTR7 0 2 C7RSM2 0 1 C7RSM1 0 0 C7RSM0 0
6 C8RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 8(RTR8). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 8 Receive Sensitivity/Monitor Select [2:0] (C8RSM[2:0]). When bits C8RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 7(RTR7). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 7 Receive Sensitivity/Monitor Select [2:0] (C7RSM[2:0]). When bits C7RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Register Address (LIUs 9-16): Bit # Name Default 7 RTR16 0 2Bh 5 C16RSM1 0 4 C16RSM0 0 3 RTR15 0 2 C15RSM2 0 1 C15RSM1 0 0 C15RSM0 0
6 C16RSM2 0
Bit 7: Receiver Transformer Turns Ratio Channel 16(RTR16). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Note that in order to use receive internal impedance termination, a 1:1 transformer must be used and this bit must be set to 1. Bit 6-4: Channel 16 Receive Sensitivity/Monitor Select [2:0] (C16RSM[2:0]). When bits C16RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17. Bit 3: Receiver Transformer Turns Ratio Channel 15(RTR15). If this bit is set the Turns Ratio is 1:1 on the Receiver Side. This bit should be set when a 1:1 Receiver transformer is used. Bit 2-0: Channel 15 Receive Sensitivity/Monitor Select [2:0] (C15RSM[2:0]). When bits C15RSM[2:0] are used to select the Receiver Sensitivity level and the Monitor Mode Resistive Gain. See Table 6-17.
Table 6-17. Receiver Sensitivity/Monitor Mode Gain Selection
RECEIVER MONITOR MODE DISABLED No flat gain No flat gain Receiver monitor mode enabled Flat gain Flat gain CNRSM [2:0], T1/E1 MODE 000 001 CnRSM [2:0] 100 101 RECEIVER SENSITIVITY (MAXIMUM LOSS) (dB) 12 18 Max cable loss 30 22.5 RECEIVER MONITOR MODE GAIN SETTINGS (dB) 0 0 Receiver monitor mode gain settings 14 20 LOSS DECLARATION LEVEL (dB) 15 21 -- 37 45.5
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 C2RSL3 0 RSL1 Receive Signal Level Indicator 1 0Ch 5 C2RSL1 0 4 C2RSL0 0 3 C1RSL3 0 2 C1RSL2 0 1 C1RSL1 0 0 C1RSL0 0
6 C2RSL2 0
Bit 7 to 4: Channel 2 Receive Signal Level [3:0] (C2RSL[3:0]). C2RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 1 Receive Signal Level [3:0] (C1RSL[3:0]). C1RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Register Address (LIUs 9-16): Bit # Name Default 7 C10RSL3 0 2Ch 5 C10RSL1 0 4 C10RSL0 0 3 C9RSL3 0 2 C9RSL2 0 1 C9RSL1 0 0 C9RSL0 0
6 C10RSL2 0
Bit 7 to 4: Channel 10 Receive Signal Level [3:0] (C10RSL[3:0]). C10RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 9 Receive Signal Level [3:0] (C9RSL[3:0]). C9RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18.
Table 6-18. Receiver Signal Level
CnRSL3 to CnRSL0 0000 0001 0010 0011 0100 0101 0110 0111 RECEIVE LEVEL (dB) T1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 E1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 C4RSL3 0
RSL2 Receive Signal Level Indicator 2 0Dh 5 C4RSL1 0 4 C4RSL0 0 3 C3RSL3 0 2 C3RSL2 0 1 C3RSL1 0 0 C3RSL0 0
6 C4RSL2 0
Bit 7 to 4: Channel 4 Receive Signal Level [3:0] (C4RSL[3:0]). C4RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 3 Receive Signal Level [3:0] (C3RSL[3:0]). C3RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Register Address (LIUs 9-16): Bit # Name Default 7 C12RSL3 0 2Dh 5 C12RSL1 0 4 C12RSL0 0 3 C11RSL3 0 2 C11RSL2 0 1 C11RSL1 0 0 C11RSL0 0
6 C12RSL2 0
Bit 7 to 4: Channel 12 Receive Signal Level [3:0] (C12RSL[3:0]). C12RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 11 Receive Signal Level [3:0] (C11RSL[3:0]). C11RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 C6RSL3 0
RSL3 Receive Signal Level Indicator 3 0Eh 5 C6RSL1 0 4 C6RSL0 0 3 C5RSL3 0 2 C5RSL2 0 1 C5RSL1 0 0 C5RSL0 0
6 C6RSL2 0
Bit 7 to 4: Channel 6 Receive Signal Level [3:0] (C6RSL[3:0]). C6RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 5 Receive Signal Level [3:0] (C5RSL[3:0]). C5RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Register Address (LIUs 9-16): Bit # Name Default 7 C14RSL3 0 2Eh 5 C14RSL1 0 4 C14RSL0 0 3 C13RSL3 0 2 C13RSL2 0 1 C13RSL1 0 0 C13RSL0 0
6 C14RSL2 0
Bit 7 to 4: Channel 14 Receive Signal Level [3:0] (C14RSL[3:0]). C14RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 13 Receive Signal Level [3:0] (C13RSL[3:0]). C13RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 C8RSL3 0 RSL4 Receive Signal Level Indicator 4 0Fh 5 C8RSL1 0 4 C8RSL0 0 3 C7RSL3 0 2 C7RSL2 0 1 C7RSL1 0 0 C7RSL0 0
6 C8RSL2 0
Bit 7 to 4: Channel 8 Receive Signal Level [3:0] (C8RSL[3:0]). C8RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 7 Receive Signal Level [3:0] (C7RSL[3:0]). C7RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Register Address (LIUs 9-16): Bit # Name Default 7 C16RSL3 0 2Fh 5 C16RSL1 0 4 C16RSL0 0 3 C15RSL3 0 2 C15RSL2 0 1 C15RSL1 0 0 C15RSL0 0
6 C16RSL2 0
Bit 7 to 4: Channel 16 Receive Signal Level [3:0] (C16RSL[3:0]). C16RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18. Bit 3 to 0: Channel 15 Receive Signal Level [3:0] (C15RSL[3:0]). C15RSL[3:0] bits provide the Receive Signal Level as shown in Table 6-18.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 BTS2 0 6 BTS1 0
BTCR Bit Error Rate Tester Control Register 10h 5 BTS0 0 4 -0 3 -0 2 -0 1 -0 0 BERTE 0
This register enables the LIU1-8 BERT. The BERT can only connect to one LIU at a time. The LIU1-8 BERT operates independently of the LIU9-16 BERT. Bit 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]) These bits BTS[2:0] select the LIU that the BERT applies too (see Table 6-19). This is only applicable if the BERTE bit is set. Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2mseconds have past, the Bit Error Rate Tester (BERT) will be enabled. The BERT Register Set should be written and read to only after being enabled. The BERT is only active for one LIU at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode with HDB3/B8ZS encoding enabled. Register Address (LIUs 9-16): Bit # Name Default 7 BTS2 0 6 BTS1 0 30h 5 BTS0 0 4 -0 3 -0 2 -0 1 -0 0 BERTE 0
This register enables the LIU9-16 BERT. The BERT can only connect to one LIU at a time. The LIU9-16 BERT operates independently of the LIU1-8 BERT. Bit 7 to 5: Bit Error Rate Transceiver Select [2:0] (BTS[2:0]) These bits BTS[2:0] select the LIU that the BERT applies too (see Table 6-20). This is only applicable if the BERTE bit is set. Bit 0: Bit Error Rate Tester Enable (BERTE). When this bit is set and 2ms have past, the Bit Error Rate Tester (BERT) will be enabled. The BERT Register Set should be written and read to only after being enabled. The BERT is only active for one LIU at a time selected by BTS[2:0]. This bit also forces the part into single-rail mode with HDB3/B8ZS encoding enabled.
Table 6-19. Bit Error Rate Transceiver Select for Channels 1-8
REGISTER ADDRESS 10h 10h 10h 10h 10h 10h 10h 10h BTS2 0 0 0 0 1 1 1 1 BTS1 0 0 1 1 0 0 1 1 BTS0 0 0 0 1 0 1 0 1 CHANNEL BERT APPLIES TO Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 6-20. Bit Error Rate Transceiver Select for Channels 9-16
REGISTER ADDRESS 30h 30h 30h 30h 30h 30h 30h 30h BTS2 0 0 0 0 1 1 1 1 BTS1 0 0 1 1 0 0 1 1 BTS0 0 0 0 1 0 1 0 1 CHANNEL BERT APPLIES TO Channel 9 Channel 10 Channel 11 Channel 12 Channel 13 Channel 14 Channel 15 Channel 16
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 BEIR8 0 6 BEIR7 0
BEIR BPV Error Insertion Register 11h 5 BEIR6 0 31h 5 BEIR14 0 4 BEIR13 0 3 BEIR12 0 2 BEIR11 0 1 BEIR10 0 0 BEIR9 0 4 BEIR5 0 3 BEIR4 0 2 BEIR3 0 1 BEIR2 0 0 BEIR1 0
Register Address (LIUs 9-16): Bit # Name Default 7 BEIR16 0 6 BEIR15 0
Bit 7 to 0: BPV Error Insertion Register n (BEIRn). A 0 to 1 transition on this bit will cause a single bipolar violation (BPV) to be inserted into the transmit data stream channel n. This bit must be cleared and set again for a subsequent error to be inserted. This is only applicable in single-rail mode.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 LVDS8 0 6 LVDS7 0
LVDS Line Violation Detect Status 12h 5 LVDS6 0 32h 5 LVDS14 0 4 LVDS13 0 3 LVDS12 0 2 LVDS11 0 1 LVDS10 0 0 LVDS9 0 4 LVDS5 0 3 LVDS4 0 2 LVDS3 0 1 LVDS2 0 0 LVDS1 0
Register Address (LIUs 9-16): Bit # Name Default 7 LVDS16 0 6 LVDS15 0
Bit 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros will cause the associated LVDSn bit to latch. This bit will be cleared on a read operation. The LVDS register captures the first violation within a three clock period window. If a second violation occurs after the first violation within the three clock period window, then the second violation will not be latched even if a read to the LVDS register was performed. Excessive zeros need to be enabled by the EZDE register for detection by this register. Code violations are only relative when in HDB3 mode and can be disabled for detection by this register by setting the CVDEB register. In dual-rail mode only bipolar violations are relevant for this register.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RCLKI8 0 6 RCLKI7 0
RCLKI Receive Clock Invert 13h 5 RCLKI6 0 33h 5 RCLKI14 0 4 RCLKI13 0 3 RCLKI12 0 2 RCLKI11 0 1 RCLKI10 0 0 RCLKI9 0 4 RCLKI5 0 3 RCLKI4 0 2 RCLKI3 0 1 RCLKI2 0 0 RCLKI1 0
Register Address (LIUs 9-16): Bit # Name Default 7 RCLKI16 0 6 RCLKI15 0
Bit 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLK for channel n is inverted. This aligns RPOS/RNEG on the falling edge of RCLK. When reset or default, RPOS/RNEG is aligned on the rising edge of RCLK.
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 TCLKI8 0 6 TCLKI7 0
TCLKI Transmit Clock Invert 14h 5 TCLKI6 0 34h 5 TCLKI14 0 4 TCLKI13 0 3 TCLKI12 0 2 TCLKI11 0 1 TCLKI10 0 0 TCLKI9 0 4 TCLKI5 0 3 TCLKI4 0 2 TCLKI3 0 1 TCLKI2 0 0 TCLKI1 0
Register Address (LIUs 9-16): Bit # Name Default 7 TCLKI16 0 6 TCLKI15 0
Bit 7 to 0: Transmit Clock Invert n (TCLKIn). When this bit is set the expected TCLK for channel n is inverted. TPOS/TNEG should be aligned on the falling edge of TCLK. When reset or default, TPOS/TNEG should be aligned on the rising edge of TCLK.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address: Bit # Name Default 7 PCLKS2 0
CCR Clock Control Register 15h 6 PCLKS1 0 5 PCLKS0 0 4 TECLKS 0 3 CLKA3 0 2 CLKA2 0 1 CLKA1 0 0 CLKA0 0
Bit 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the PLL. If a LOS is detect for the channel that RCLK is recovered from, the PLL will switch to MCLK until the LOS is cleared. When the LOS is cleared RCLK will be used again. See Table 6-21 for RCLK selection. MC.PCLKI[1:0] must be set to `01' or `10' in order for these settings to take affect. Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is reset the T1/E1 clock rate is 1.544MHz Bit 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See Table 6-22 for available frequencies. For best jitter performance, select MCLK as the source for CLKA and input a 2.048 MHz MCLK.
Table 6-21. PLL Clock Select
PCLKS2 TO PCLKS0 000 001 010 011 100 101 110 111 PLL CLOCK SELECTED MC.PCLKI[1:0]=01 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 PLL CLOCK SELECTED MC.PCLKI[1:0]=10 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 RCLK16
Table 6-22. Clock A Select
CLKA3 TO CLKA0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CLKA (Hz) 2.048M 4.096M 8.192M 16.384M 1.544M 3.088M 6.176M 12.352M 1.536M 3.072M 6.144M 12.288M 32k 64k 128k 256k
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Bit # Name Default 7 RDULR8 0
RDULR RCLK Disable Upon LOS Register 16h 5 RDULR6 0 4 RDULR5 0 3 RDULR4 0 2 RDULR3 0 1 RDULR2 0 0 RDULR1 0
6 RDULR7 0 36h
Register Address (LIUs 9-16): Bit # Name Default 7 RDULR16 0
6 RDULR15 0
5 RDULR14 0
4 RDULR13 0
3 RDULR12 0
2 RDULR11 0
1 RDULR10 0
0 RDULR9 0
Bit 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for channel n is disabled upon a Loss of signal and set as a low output. When reset or default, RCLK will switch to MCLK upon a loss of signal within 10ms.
Register Name: Register Description: Register Address: Bit # Name Default 7 -- 0 6 -- 0
GISC Global Interrupt Status Control 1Eh 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 INTM 0 0 CWE 0
Bit 0: Clear-On-Write Enable (CWE). When this bit is set the Clear on Write is enabled for all the Latched Interrupt Status registers. The host processor has to write a 1 to the Latched Interrupt Status Register bit position before the particular bit will be cleared. Default for all the Latched interrupt Status registers is to clear on a read. Bit 1: INT Pin Mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low when active. 0 = Pin is high impedance when not active 1 = Pin drives high when not active
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
6.1.4
BERT Registers
BCR BERT Control Register 00h 20h 5 RNPL 0 4 RPIC 0 3 MPR 0 2 APRD 0 1 TNPL 0 0 TPIC 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 PMUM 0 6 LPMU 0
Bit 7: Performance Monitoring Update Mode (PMUM). When 0, a performance monitoring update is initiated by the LPMU register bit. When 1, a performance monitoring update is initiated by the receive performance monitoring update signal (RPMU). Note: If RPMU or LPMU is one, changing the state of this bit may cause a performance monitoring update to occur. Bit 6: Local Performance Monitoring Update (LPMU). This bit causes a performance monitoring update to be initiated if local performance monitoring update is enabled (PMUM = 0). A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second performance monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the PMS bit goes high, an update might not be performed. This bit has no affect when PMUM=1. Bit 5: Receive New Pattern Load (RNPL). A zero to one transition of this bit will cause the programmed test pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces the receive pattern generator out of the "Sync" state which causes a resynchronization to be initiated. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four RXCK clock cycles after this bit transitions from 0 to 1. Bit 4: Receive Pattern Inversion Control (RPIC). When 0, the received incoming data stream is not altered. When 1, the received incoming data stream is inverted. Bit 3: Manual Pattern Resynchronization (MPR). A zero to one transition of this bit will cause the receive pattern generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for another resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator out of the "Sync" state. Bit 2: Automatic Pattern Resynchronization Disable (APRD) - When 0, the receive pattern generator will automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is prevented by not allowing the receive pattern generator to automatically exit the "Sync" state. Bit 1: Transmit New Pattern Load (TNPL). A zero to one transition of this bit will cause the programmed test pattern (QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this bit transitions from 0 to 1. Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered. When 1, the transmit outgoing data stream is inverted.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -- 0 6 QRSS 0 BPCR1 BERT Pattern Configuration Register 1 02h 22h 5 PTS 0 4 PLF4 0 3 PLF3 0 2 PLF2 0 1 PLF1 0 0 PLF0 0
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a 20 17 generating polynomial of x + x + 1. The output of the pattern generator will be forced to one if the next fourteen output bits are all zero. Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive pattern. Bit 4-0: Pattern Length Feedback (PLF[4:0]). These five bits control the "length" feedback of the pattern generator. The "length" feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -- 0 6 -- 0
BPCR 2 BERT Pattern Configuration Register 2 03h 23h 5 -- 0 4 PTF4 0 3 PTF3 0 2 PTF2 0 1 PTF1 0 0 PTF0 0
Bit 4-0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS "tap" feedback of the pattern generator. The "tap" feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BSP7 0 6 BSP6 0 BSPR1 BERT Seed/Pattern Register #1 04h 24h 5 BSP5 0 4 BSP4 0 3 BSP3 0 2 BSP2 0 1 BSP1 0 0 BSP0 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BSP15 0 6 BSP14 0
BSPR2 BERT Seed/Pattern Register #2 05h 25h 5 BSP13 0 4 BSP12 0 3 BSP11 0 2 BSP10 0 1 BSP9 0 0 BSP8 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BSP23 0 6 BSP22 0
BSPR3 BERT Seed/Pattern Register #3 06h 26h 5 BSP21 0 4 BSP20 0 3 BSP19 0 2 BSP18 0 1 BSP17 0 0 BSP16 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BSP31 0 6 BSP30 0
BSPR4 BERT Seed/Pattern Register #4 07h 27h 5 BSP29 0 4 BSP28 0 3 BSP27 0 2 BSP26 0 1 BSP25 0 0 BSP24 0
BERT Seed/Pattern (BSP[31:0]). These 32 bits are the programmable seed for a transmit PRBS pattern, or the programmable pattern for a transmit or receive repetitive pattern. BSP(31) will be the first bit output on the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) will be the first bit input on the receive side for a 32-bit repetitive pattern.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -0 6 -0
TEICR Transmit Error Insertion Control Register 08h 28h 5 TEIR2 0 4 TEIR1 0 3 TEIR0 0 2 BEI 0 1 TSEI 0 0 MEIMS 0
Bit 5-3: Transmit Error Insertion Rate (TEIR[2:0]). These three bits indicate the rate at which errors are inserted n in the output data stream. One out of every 10 bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0 th disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10 bit being inverted. A TEIR[2:0] th value of 2 results in every 100 bit being inverted. Error insertion starts when this register is written to with a TEIR[2:0] value that is nonzero. If this register is written to during the middle of an error insertion process, the new error rate will be started after the next error is inserted. Bit 2: Bit Error Insertion Enable (BEI). When 0, single bit error insertion is disabled. When 1, single bit error insertion is enabled. Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if manual error insertion is disabled (MEIMS = 0) and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error will be inserted. Bit 0: Manual Error Insert Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit. When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is one, changing the state of this bit may cause a bit error to be inserted.
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -- 0 6 -- 0
BSR BERT Status Register 0Ch 2Ch 5 -- 0 4 -- 0 3 PMS 0 2 -- 0 1 BEC 0 0 OOS 0
Bit 3: Performance Monitoring Update Status (PMS). This bit indicates the status of the receive performance monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS is asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM=1) goes low. Bit 1: Bit Error Count (BEC). When 0, the bit error count is zero. When 1, the bit error count is one or more. Bit 0: Out Of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -- 0 6 -- 0 BSRL BERT Status Register Latched 0Eh 2Eh 5 -- 0 4 -- 0 3 PMSL 0 2 BEL 0 1 BECL 0 0 OOSL 0
Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from 0 to 1. A read operation clears this bit. Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected. A read operation clears this bit. Bit 1: Bit Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1. A read operation clears this bit. Bit 0: Out Of Synchronization Latched (OOSL). This bit is set when the OOS bit changes state. A read operation clears this bit.
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 -- 0 6 -- 0
BSRIE BERT Status Register Interrupt Enable 10h 30h 5 -- 0 4 -- 0 3 PMSIE 0 2 BEIE 0 1 BECIE 0 0 OOSIE 0
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the PMSL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 2: Bit Error Interrupt Enable (BEIE). This bit enables an interrupt if the BEL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set. 0 = interrupt disabled 1 = interrupt enabled
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BEC7 0 6 BEC6 0
RBECR1 Receive Bit Error Count Register #1 14h 34h 5 BEC5 0 4 BEC4 0 3 BEC3 0 2 BEC2 0 1 BEC1 0 0 BEC0 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BEC15 0 6 BEC14 0
RBECR2 Receive Bit Error Count Register #1 15h 35h 5 BEC13 0 4 BEC12 0 3 BEC11 0 2 BEC10 0 1 BEC9 0 0 BEC8 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BEC23 0 6 BEC22 0
RBECR3 Receive Bit Error Count Register #2 16h 36h 5 BEC21 0 4 BEC20 0 3 BEC19 0 2 BEC18 0 1 BEC17 0 0 BEC16 0
Bit Error Count (BEC[23:0]). These twenty-four bits indicate the number of bit errors detected in the incoming data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit error counter will not incremented when an OOS condition exists.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BC7 0 6 BC6 0 RBCR1 Receive Bit Count Register #1 18h 38h 5 BC5 0 4 BC4 0 3 BC3 0 2 BC2 0 1 BC1 0 0 BC0 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 15 BC15 0 14 BC14 0
RBCR2 Receive Bit Count Register #2 19h 39h 13 BC13 0 12 BC12 0 11 BC11 0 10 BC10 0 9 BC9 0 8 BC8 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 7 BC23 0 6 BC22 0
RBCR3 Receive Bit Count Register #3 1Ah 3Ah 5 BC21 0 4 BC20 0 3 BC19 0 2 BC18 0 1 BC17 0 0 BC16 0
Register Name: Register Description: Register Address (LIUs 1-8): Register Address (LIUs 9-16): Bit # Name Default 15 BC31 0 14 BC30 0
RBCR4 Receive Bit Count Register #4 1Bh 3Bh 13 BC29 0 12 BC28 0 11 BC27 0 10 BC26 0 9 BC25 0 8 BC24 0
Bit Count (BC[31:0]). These thirty-two bits indicate the number of bits in the incoming data stream. This count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter will not incremented when an OOS condition exists.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
7 JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT
The DS26324 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26324 contains the following as required by IEEE 1149.1 Standard Test-Access Port and Boundary-Scan Architecture: * * * * * * Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: TRSTB, TCLK, TMS, TDI, and TDO. See the pin descriptions for details. For the latest BSDL files go to www.maxim-ic.com/tools/bsdl/ and search for DS26324.
Figure 7-1. JTAG Functional Block Diagram
BOUNDARY SCAN REGISTER
INDENTIFICATION REGISTER BYPASS REGISTER
MUX
INSTRUCTION REGISTER
TEST ACCESS PORT CONTROLLER
+V +V +V
SELECT OUTPUT ENABLE
10kW
10kW
10kW
TDI
TMS
TCLK
TRSTB
TDO
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
7.1
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCLK. The state diagram is shown in Figure 7-2. Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. This state is automatically entered during power-up. This state is entered from any state if the TMS is held high for at least 5 clocks. Run-Test-Idle The run-test-idle is used between scan operations or during specific tests. The instruction register and test registers will remain idle. The controller remains in this state when TMS is held low. When the TMS is high and rising edge of TCLK is applied the controller moves to the Select-DR-Scan State. Select-DR-Scan All test registers retain their previous state. With TMS LOW, a rising edge of TCLK moves the controller into the capture-DR state and will initiate a scan sequence. TMS HIGH during a rising edge on TCLK moves the controller to the select-IR-scan state. Capture-DR Data can be parallel-loaded into the test-data registers if the current instruction is EXTEST or SAMPLE/PRELOAD. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of TCLK, the controller will go to the shift-DR state if TMS is LOW or it will go to the exit1-DR state if TMS is HIGH. Shift-DR The test-data register selected by the current instruction will be connected between TDI and TDO and will shift data one stage towards its serial output on each rising edge of TCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state. When the TAP Controller is in this state and a rising edge of TCLK is applied, the controller enters the EXIT1-DR state if TMS is high or remains in SHIFT-DR state if TMS is low. Exit1-DR While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the scanning process, if TMS is HIGH. A rising edge on TCLK with TMS LOW will put the controller in the Pause-DR state. Pause-DR Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while TMS is LOW. A rising edge on TCLK with TMS HIGH will put the controller in the exit2-DR state. Exit2-DR A rising edge on TCLK with TMS HIGH while in this state will put the controller in the update-DR state and terminate the scanning process. A rising edge on TCLK with TMS LOW will enter the shift-DR state.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit Update-DR A falling edge on TCLK while in the update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With TMS LOW, a rising edge on TCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. TMS HIGH during a rising edge on TCLK puts the controller back into the Test-logicreset state. Capture-IR The capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCLK. If TMS is HIGH on the rising edge of TCLK, the controller will enter the exit1-IR state. If TMS is LOW on the rising edge of TCLK, the controller will enter the shift-IR state. Shift-IR In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one stage for every rising edge of TCLK towards the serial output. The parallel registers as well as all test registers remain at their previous states. A rising edge on TCLK with TMS HIGH will move the controller to the exit1-IR state. A rising edge on TCLK with TMS LOW will keep the controller in the shift-IR state while moving data one stage thorough the instruction shift register. Exit1-IR A rising edge on TCLK with TMS LOW will put the controller in the pause-IR state. If TMS is HIGH on the rising edge of TCLK, the controller will enter the update-IR state and terminate the scanning process. Pause-IR Shifting of the instruction shift register is halted temporarily. With TMS HIGH, a rising edge on TCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if TMS is LOW during a rising edge on TCLK. Exit2-IR A rising edge on TCLK with TMS High will put the controller in the Update-IR state. The controller will loop back to shift-IR if TMS is LOW during a rising edge of TCLK in this state. Update-IR The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCLK with TMS LOW will put the controller in the run-test-idle state. With TMS HIGH, the controller will enter the select-DR-scan state.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 7-2. TAP Controller State Diagram
Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1
1
0
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
7.2
Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between TDI and TDO. While in the shift-IR state, a rising edge on TCLK with TMS LOW will shift the data one stage towards the serial output at TDO. A rising edge on TCLK in the exit1-IR state or the exit2-IR state with TMS HIGH will move the controller to the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26324 and its respective operational binary codes are shown in Table 7-1.
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION EXTEST HIGHZ CLAMP SAMPLE/PRELOAD IDCODE BYPASS SELECTED REGISTER Boundary Scan Bypass Bypass Boundary Scan Device Identification Bypass INSTRUCTION CODES 000 010 011 100 110 111
EXTEST This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between TDI and TDO. The Capture-DR will sample all digital inputs into the boundary scan register. HIGHZ All digital outputs of the device will be placed in a high-Z state. The BYPASS register will be connected between TDI and TDO. CLAMP All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between TDI and TDO. The outputs will not change during the CLAMP instruction. SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via TDI using the shift-DR state. IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of TCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via TDO. During test-logic-reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a 1 in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 7-2. Table 7-3 lists the device ID code for the DS26324. BYPASS When the BYPASS instruction is latched into the parallel instruction register, TDI connects to TDO through the onebit bypass test register. This allows data to pass from TDI to TDO not affecting the device's normal operation.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 7-2. ID Code Structure
MSB Version Contact Factory 4 bits Device ID 16 bits JEDEC 00010100001 LSB 1 1
Table 7-3. Device ID Codes
DEVICE DS26324 16-BIT ID 003C h
7.3
Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS26324 design. This test register is the identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP controller.
7.4
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length.
7.5
Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a short path between TDI and TDO.
7.6
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state. See Table 7-2 and Table 7-3 for more information about bit usage.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
8 DC ELECTRICAL CHARACTERIZATION
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)....................................................-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS....................................................................-0.3V to +3.63V Operating Temperature Range for DS26324G..........................................................................0C to +70C Operating Temperature Range for DS26324GN......................................................................-40C to +85C Storage Temperature.......................................................................................................-55C to +125C Soldering Temperature...................................................................See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
Table 8-1. DC Pin Logic Levels RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C for DS26324GN.) PARAMETER SYMBOL Logic 1 VIH Logic 0 Supply VIL VDD MIN 2.0 -0.3 3.135 3.3 TYP MAX 5.5 +0.8 3.465 UNITS V V V NOTES
Table 8-2. Pin Capacitance CAPACITANCE
(TA = +25C) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP 7 7 MAX UNITS pF pF NOTES
Table 8-3. Supply Current and Output Voltage DC CHARACTERISTICS
(VDD = 3.135 to 3.465V, TA = -40C to +85C.) PARAMETER SYMBOL MIN Supply Current at 3.465V IDD Supply Current at 3.3V Input Leakage Tri-State Output Leakage Output Voltage (Io = -4.0mA) Output Voltage (Io = +4.0mA)
Note 1: Note 2:
TYP 500
MAX 1100 +10.0 +10.0 0.4
UNITS mA mA mA V V
NOTES 1, 2
IIL IOL VOH VOL
-10.0 -10.0 2.4
RCLK1-n = TCLK1-n = 1.544MHz. Supply current with all ports active, TTIP and TRING driving a 25W load, for an all-ones data density.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
9 AC TIMING CHARACTERISTICS
9.1 Line Interface Characteristics
Table 9-1. Transmitter Characteristics
PARAMETER E1 75W Output Mark Amplitude E1 120W VM T1 100W T1 110W Output Zero Amplitude Transmit Amplitude Variation with Supply Transmit Path Delay Single Rail Dual Rail VS 2.4 2.4 -0.3 -1 8 3 3.0 3.0 3.6 3.6 +0.3 +1 V % UI 1 SYMBOL MIN 2.14 2.7 TYP 2.37 3.0 MAX 2.6 3.3 UNITS V NOTES
Table 9-2. Receiver Characteristics
PARAMETER Cable Attenuation Analog Loss-of-Signal Threshold Hysteresis Short-Haul Mode Allowable Zeros Before Loss SYMBOL Attn 200 100 192 192 2048 24 Allowable Ones Before Loss Single Rail Dual Rail 192 192 Receive Path Delay
Note 1: Note 2: Note 3:
MIN
TYP
MAX 12
UNITS dB mV
NOTES
1
2
3
8 3
UI
Measured at the RRING and RTIP pins. 192 zeros for T1 and T1.231 Specification Compliance; 192 zeros for E1 and G.775 Specification Compliance; 2048 zeros for ETSI 300 233 compliance. 24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETSI 300 233.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
9.2
Parallel Host Interface Timing Characteristics
Table 9-3. Intel Read Mode Characteristics
(VDD = 3.3V 5%, TJ = -40C to +125C.) SIGNAL NAME(S) RDB CSB CSB AD[7:0] A[5:0] D[7:0], AD[7:0] D[7:0], AD[7:0] RDYB RDYB AD[7:0] ALE D[7:0] A[5:0] RDYB RDYB
Note 1:
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
DESCRIPTION Pulse width if not using RDYB Setup time to RDB Hold time from RDB Setup time to ALE Hold time from RDB Delay time RDB, CSB active Deassert delay from RDB, CSB inactive Enable delay time from CSB active Disable delay time from the CSB inactive Hold time from ALE Pulse width Output Delay from ALE Latched Setup time to RDB Delay time from RDB Active output delay time from RDB
MIN 40 0 0 2 0
TYP MAX UNITS NOTES ns ns ns ns ns 40 ns ns ns ns ns ns 40 ns ns ns 35 ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2
20 20 15
3 5
10 0 10
The input/output timing reference level for all signals is VDD/2.
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-1. Intel Nonmuxed Read Cycle
t2
CSB
t3
RDB
t1
ALE=(1)
t13
ADDRESS
t5
A[5:0]
t6
D[7:0] DATA OUT
t7
t8
RDYB
t14
t9
t15
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DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-2. Intel Mux Read Cycle
t2
CSB
t3
RDB
t1 t11
t12
ALE
t6 t4
AD[7:0] ADDRESS
t10
DATA OUT
t7
t8
RDYB
t14
t9
t15
95 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 9-4. Intel Write Cycle Characteristics
(VDD = 3.3V 5%, TJ = -40C to +125C.) SIGNAL SYMBOL DESCRIPTION NAME(S) WRB t1 Pulse width CSB CSB AD[7:0] A[5:0] D[7:0], AD[7:0] D[7:0], AD[7:0] RDYB RDYB RDYB RDYB ALE AD[7:0] A[5:0]
Note 1:
MIN 40 0 0 2 0 10 5
TYP
MAX
UNITS ns ns ns ns ns ns ns
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14
Setup time to WRB Hold time to WRB Setup time to ALE Hold time from WRB Input setup time to WRB Input hold time to WRB Enable delay from CSB active Delay time from WRB active Delay time from WRB inactive Disable delay time from CSB inactive Pulse width Hold time from ALE inactive Valid address to WRB inactive
20 10 0 15 5 3 35
ns ns ns ns ns ns ns
The input/output timing reference level for all signals is VDD/2.
96 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-3. Intel Nonmux Write Cycle
t2
CSB
t3
WRB
t1
ALE=(1)
t14
ADDRESS
t5
A[5:0]
t6
D[7:0] WRITE DATA
t7
t8
RDYB
t10
t11
t9
97 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-4. Intel Mux Write Cycle
t2
CSB
t3
WRB
t1 t12
ALE
t13 t4
AD[7:0] ADDRESS
t6
t7
WRITE DATA
t8
RDYB
t10
t11
t9
98 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 9-5. Motorola Read Cycle Characteristics
(VDD = 3.3V 5%, TJ = -40C to +125C.) SIGNAL SYMBOL DESCRIPTION NAME(S) DS t1 Pulse width CSB CSB RWB RWB AD[7:0] AD[7:0] AD[7:0], D[7:0] AD[7:0], D[7:0] ACKB ACKB ACKB ACKB A[5:0] A[5:0]
Note 1:
MIN 40 0 0 0 0 2 3
TYP
MAX
UNITS ns ns ns ns ns ns ns
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
t2 t3 t4 t5 t6 t7 t8 t10 t11 t12 t13 t14 t15 t16
Setup time to DSB active Hold time from DSB inactive Setup time to DSB active Hold time from DSB inactive Setup time to ASB active Hold time to ASB inactive Output delay time from DSB active Output valid delay time from DSB inactive Output delay time from CSB inactive Output delay time from DSB inactive Enable output delay time from DSB active Output delay time from DSB active Hold time from DSB inactive Setup time to DSB active
40 2 20 15 0 20 10 0 10 35
ns ns ns ns ns ns ns ns
The input/output timing reference level for all signals is VDD/2.
99 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-5. Motorola Nonmux Read Cycle
t3
CSB
t2
t4 RWB
t5
DSB
t1
ASB=(1)
t16
ADDRESS
t15
A[5:0]
t8
D[7:0] DATA OUT
t10
t12
ACKB
t11
t13
t14
100 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-6. Motorola Mux Read Cycle
CSB
t2
t3
t4
RWB
t5
DSB
t1 t14
ASB
t6
AD[7:0]
t7 t8 ADDRESS DATA OUT
t10
t12
ACKB
t11
t13
t14
101 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 9-6. Motorola Write Cycle Characteristics
(VDD = 3.3V 5%, TJ = -40C to +125C.) SIGNAL SYMBOL NAME(S) DSB t1 Pulse width CSB CSB RWB RWB AD[7:0] AD[7:0] AD[7:0], D[7:0] AD[7:0], D[7:0] A[5:0] ACKB ACKB ACKB ACKB A[5:0]
Note 1:
DESCRIPTION
MIN 35 0 0 0 0 2 3 10 5 10
TYP
MAX UNITS NOTES ns ns ns ns ns ns ns ns ns ns 15 ns ns 20 ns ns ns 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15
Setup time to DSB active Hold time from DSB inactive Setup time to DSB active Hold time to DSB inactive Setup time to ASB active Hold time from ASB active Setup time to DSB inactive Hold time from DSB inactive Setup time to DSB active Output delay from CSB inactive Output delay from DSB inactive Output enable delay time from DSB active Output delay time from DSB active Hold time from DSB
0 10 0
The input/output timing reference level for all signals is VDD/2.
102 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-7. Motorola Nonmux Write Cycle
CSB
t2
t3
t4 RWB
t5
DSB
t1
ASB=(1)
t10
ADDRESS
t15
A[5:0]
t8
D[7:0] WRITE DATA
t9
t12
ACKB
t11
t13
t14
103 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Figure 9-8. Motorola Mux Write Cycle
t2 t3
CSB
t4 RWB
t5
DSB
t1
t13
ASB
t6
AD[7:0]
t7
t8
WRITE DATA
t9
ADDRESS
t12
ACKB
t11 t13 t14
104 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
9.3
Serial Port
Table 9-7. Serial Port Timing Characteristics
PARAMETER SCLK High Time SCLK Low Time Active CSB to SCLK Setup Time Last SCLK to CSB Inactive Time CSB Idle Time SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Falling Edge to SDO High-Z (CLKE = 0); CSB rising to SDO High-Z (CLKE =1) SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 MIN 25 25 50 50 50 5 5 100 TYP MAX UNITS ns ns ns ns ns ns ns ns NOTES
Figure 9-9. Serial Bus Timing Write Operation
t5
CSB
t3 t4
t1 t2
SCLK
t6
t7
SDI
LSB
MSB
Figure 9-10. Serial Bus Timing Read Operation with CLKE = 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK CSB SDO
t4 t8
Figure 9-11. Serial Bus Timing Read Operation with CLKE = 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SCLK CSB SDO
t4 t8
105 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
9.4
System Timing
Table 9-8. Transmitter System Timing
PARAMETER TPOS, TNEG Setup Time with Respect to TCLK Falling Edge TPOS, TNEG Hold Time with Respect to TCLK Falling Edge TCLK Pulse-Width High TCLK Pulse-Width Low TCLK Period TCLK Rise Time TCLK Fall Time SYMBOL t1 t2 t3 t4 t5 648 t6 t7 25 25 ns ns MIN 40 40 75 75 488 ns TYP MAX UNITS ns ns ns ns NOTES
Figure 9-12. Transmitter Systems Timing
t5 t7 TCLK t1 TPO S , TN EG t2 t6 t3 t4
106 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
Table 9-9. Receiver System Timing
PARAMETER Delay RCLK to RPOS, RNEG Valid Delay RCLK to CV Valid in Single-Rail Mode RCLK Pulse-Width High RCLK Pulse-Width Low RCLK Period SYMBOL t1 t2 t3 t4 t5 200 200 488 648 MIN TYP MAX 50 50 UNITS ns ns ns ns ns NOTES
Figure 9-13. Receiver Systems Timing
RCLK 1 t3 RCLK 2 t1 RPOS,RNEG t2 CV Notes: 1) CLKE = 1. 2) CLKE = 0. BPV/ EXZ/ CV BPV/ EXZ/ CV t5 t4
107 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
9.5
JTAG Timing
Table 9-10. JTAG Timing Characteristics
PARAMETER TCK Period TMS and TDI Setup to TCK TMS and TDI Hold to TCK TCK to TDO Hold SYMBOL t1 t2 t3 t4 MIN 100 25 25 50 TYP MAX UNITS ns ns ns ns NOTES
Figure 9-14. JTAG Timing
t1
TC K t2 TM S TD I TD O
t3
t4
108 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
10 PIN CONFIGURATION
Figure 10-1. 256-Ball TEBGA
1 A B C D E F G H J K L M N P R T
RTIP1
2
RRING1
3
MODESEL
4
RTIP16
5
VDDT16
6
TTIP16
7
TTIP15
8
VDDT15
9
RTIP15
10
VDDT14
11
TTIP14
12
TTIP13
13
VDDT13
14
RTIP14
15
TDO
16
RTIP13
AVDD
AVSS
MOTEL
RRING16
RSTB
TRING16
TRING15
LOS14
RRING15
LOS13
TRING14
TRING13
TMS
RRING14
TDI
RRING13
RTIP2
RRING2
TNEG1
A4
TNEG16
TNEG15
RNEG15
RPOS15
RNEG14
RPOS14
TCLK13
RPOS13
SDO/RDY/ACKB
TPOS12
AVSS
AVDD
VDDT1
LOS1
RCLK1
GNDT1
TPOS16
GNDT16
INTB
GNDT15
GNDT14
GNDT13
TCLK16
TCLK14
GNDT12
TCK
RRING12
RTIP12
TTIP1
TRING1
RNEG1
A5
RPOS16
RCLK16
TPOS14
RCLK13
RCLK14
RNEG13
LOS15
TCLK12
TNEG12
RPOS12
TRSTB
VDDT12
TTIP2
TRING2
RPOS2
RPOS1
TCLK1
TPOS1
TNEG14
RCLK15
TPOS13
LOS16
RNEG12
RCLK12
RNEG11
TCLK11
TRING12
TTIP12
VDDT2
LOS2
A2
TCLK2
RNEG2
RCLK2
TPOS2
TNEG13
TCLK3
TNEG4
TPOS11
RPOS11
RCLK11
SDI/WRB/DSB
TRING11
TTIP11
RTIP3
RRING3
A1
GNDT2
A3
TCLK4
AVDD
DVDD
DVSS
AVSS
TNEG11
MCLK
GNDT11
RDB/RWB
LOS12
VDDT11
VDDT3
LOS3
RNEG16
GNDT3
TNEG3
TPOS3
AVSS
DVSS
DVDD
AVDD
TPOS10
TNEG10
GNDT10
TNEG2
RRING11
RTIP11
TTIP3
TRING3
RCLK3
RNEG3
RCLK4
TPOS4
D3
RPOS5
TNEG8
RNEG8
TCLK9
TCLK10
RPOS10
RCLK10
LOS11
VDDT10
TTIP4
TRING4
RPOS3
RPOS4
D4
D0
RNEG5
TCLK6
TPOS5
TCLK7
TPOS9
TNEG9
RCLK9
RNEG10
TRING10
TTIP10
VDDT4
LOS4
RNEG4
D5
D1
TNEG5
TCLK5
RCLK6
RPOS6
RNEG6
TPOS8
RPOS8
RNEG9
RPOS9
TRING9
TTIP9
RTIP4
RRING4
D7
GNDT4
TPOS6
GNDT5
TCLK15
GNDT6
GNDT7
A0
GNDT8
TPOS15
GNDT9
SCLK/ALE/ASB
LOS10
VDDT9
AVDD
AVSS
D6
D2
RCLK5
TNEG6
TNEG7
RPOS7
TCLK8
RCLK7
RNEG7
TPOS7
RCLK8
CSB
RRING10
RTIP10
RRING5
LOS5
RRING6
LOS7
TRING5
TRING6
LOS8
RRING7
DVSS
TRING7
TRING8
OE
RRING8
LOS9
AVSS
AVDD
RTIP5
LOS6
RTIP6
VDDT5
TTIP5
TTIP6
VDDT6
RTIP7
VDDT7
TTIP7
TTIP8
VDDT8
RTIP8
CLKE/MUX
RRING9
RTIP9
109 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
11 PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
110 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
12 THERMAL INFORMATION
Table 12-1. Thermal Characteristics
PARAMETER Power Dissipation in Package Ambient Temperature Junction Temperature Theta-JA (qJA) in Still Air Conduction Theta-JC (qJC) Conduction Theta-JB (qJB) Conduction Theta-JA (qJA) in Forced Air Theta-JA (qJA) in Forced Air Theta-JA (qJA) in Forced Air
Note 1: Note 2: Note 3:
MIN -40C
TYP 1.4W
MAX 2.5W +85C +125C
V (m/s)
NOTES 3 1
+16.6C/W +3.0C/W +7.5C/W +15.0C/W +14.6C/W +14.0C/W
0
2
0.75 1.25 2.5
The package is mounted on a four-layer JEDEC standard test board. Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board. The typical wattage is with 50% ones and LB00.
111 of 112
DS26324 3.3V, 16-Channel, E1/T1/J1, Short-Haul Line Interface Unit
13 REVISION HISTORY
DATE 070105 DESCRIPTION Original release.
112 of 112
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2005 Maxim Integrated Products * Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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